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multiformat video encoder six, 11-bit, 297 mhz dacs ADV7342/adv7343 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features 74.25 mhz 20-/30-bit high definition input support compliant with smpte 274m (1080i), 296m (720p), and 240m (1035i) 6, 11-bit, 297 mhz video dacs 16 (216 mhz) dac oversampling for sd 8 (216 mhz) dac oversampling for ed 4 (297 mhz) dac oversampling for hd 37 ma maximum dac output current ntsc m, pal b/d/g/h/i/m/n, pal 60 support ntsc and pal square pixel operation (24.54 mhz/29.5 mhz) multiformat video input support 4:2:2 ycrcb (sd, ed, and hd) 4:4:4 ycrcb (ed and hd) 4:4:4 rgb (sd, ed, and hd) multiformat video output support composite (cvbs) and s-video (y/c) component yprpb (sd, ed, and hd) component rgb (sd, ed, and hd) macrovision? rev 7.1.l1 (sd) and rev 1.2 (ed) compliant simultaneous sd and ed/hd operation eia/cea-861b compliance support programmable features luma and chroma filter responses vertical blanking interval (vbi) subcarrier frequency (f sc ) and phase luma delay copy generation management system (cgms) closed captioning and wide screen signaling (wss) integrated subcarrier locking to external video source complete on-chip video timing generator on-chip test pattern generation on-board voltage reference (optional external input) serial mpu interface with dual i 2 c? and spi? compatibility 3.3 v analog operation 1.8 v digital operation 3.3 v i/o operation temperature range: ?40c to +85c applications dvd recorders and players high definition blu-ray dvd players hd-dvd players functional block diagram r gnd_io vdd_io 10-bit sd video data 20-bit ed/hd video data s_hsync p_hsync p_vsync p_blank s_vsync 11-bit dac 1 dac 1 11-bit dac 2 dac 2 11-bit dac 3 dac 3 11-bit dac 4 dac 4 11-bit dac 5 dac 5 11-bit dac 6 dac 6 multiplexer reference and cable detect 16x/4x oversampling dac pll video timing generator power management control clkin (2) pv dd pgnd ext_lf (2) v ref comp (2) r set (2) ed/hd input deinterleave programmable hdtv filters sharpness and adaptive filter control ycbcr hdtv test pattern generator ycbcr to rgb matrix g/b rgb async bypass rgb dgnd (2) v dd (2) scl/ mosi sda/ sclk a lsb/ spi_ss sfl/ miso mpu port subcarrier frequency lock (sfl) yuv to ycrcb/ rgb programmable chrominance filter add burst rgb/ycrcb to yuv matrix 4:2:2 to 4:4:4 hd ddr deinterleave sin/cos dds block 16 filter 16 filter 4 filter agnd v aa add sync vbi data service insertion programmable luminance filter 06399-001 ADV7342/adv7343 figure 1. protected by u.s. patent numbers 5,343,196 and 5,442, 355 and other intellectu al property rights. protected by u.s. patent numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights.
ADV7342/adv7343 rev. 0 | page 2 of 88 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 detailed features .............................................................................. 4 general description ......................................................................... 4 specifications..................................................................................... 5 power supply and voltage specifications.................................. 5 voltage reference specifications ................................................ 5 input clock specifications .......................................................... 5 analog output specifications..................................................... 6 digital input/output specifications........................................... 6 digital timing specifications ..................................................... 7 mpu port timing specifications ............................................... 8 power specifications .................................................................... 8 video performance specifications ............................................. 9 timing diagrams............................................................................ 10 absolute maximum ratings.......................................................... 17 thermal resistance .................................................................... 17 esd caution................................................................................ 17 pin configuration and function descriptions........................... 18 typical performance characteristics ........................................... 20 mpu port description................................................................... 25 i 2 c operation.............................................................................. 25 spi operation.............................................................................. 26 register map access....................................................................... 27 register programming............................................................... 27 subaddress register (sr7 to sr0) ............................................ 27 input configuration ....................................................................... 44 standard definition only.......................................................... 44 enhanced definition/high definition only .......................... 45 simultaneous standard definition and enhanced definition/high definition....................................................... 45 enhanced definition only (at 54 mhz) ................................. 46 output configuration .................................................................... 47 features ............................................................................................ 48 output oversampling ................................................................ 48 ed/hd nonstandard timing mode........................................ 48 ed/hd timing reset ................................................................ 49 sd subcarrier frequency lock, subcarrier phase reset, and timing reset ............................................................................... 49 sd vcr ff/rw sync ................................................................ 50 vertical blanking interval ......................................................... 50 sd subcarrier frequency registers.......................................... 50 sd noninterlaced mode............................................................ 51 sd square pixel mode ............................................................... 51 filters............................................................................................ 52 ed/hd test pattern color controls ....................................... 53 color space conversion matrix ............................................... 53 sd luma and color control..................................................... 54 sd hue adjust control.............................................................. 55 sd brightness detect ................................................................. 55 sd brightness control............................................................... 55 sd input standard auto detection.......................................... 55 double buffering ........................................................................ 56 programmable dac gain control .......................................... 56 gamma correction .................................................................... 56 ed/hd sharpness filter and adaptive filter controls......... 58 ed/hd sharpness filter and adaptive filter application examples...................................................................................... 59 sd digital noise reduction...................................................... 60 sd active video edge control ................................................. 61 external horizontal and vertical synchronization control ........................................................... 63 low power mode........................................................................ 64 cable detection .......................................................................... 64 dac auto power-down............................................................ 64 pixel and control port readback............................................. 64 reset mechanism........................................................................ 64 printed circuit board layout and design .................................. 65 dac configurations.................................................................. 65 voltage reference ....................................................................... 65 video output buffer and optional output filter.................. 65 printed circuit board (pcb) layout ....................................... 66 typical application circuit....................................................... 68 appendix 1copy generation management system .............. 69 sd cgms .................................................................................... 69 ed cgms.................................................................................... 69 hd cgms................................................................................... 69 cgms crc functionality ........................................................ 69
ADV7342/adv7343 rev. 0 | page 3 of 88 appendix 2sd wide screen signaling .....................................72 appendix 3sd closed captioning............................................73 appendix 4internal test pattern generation ..........................74 sd test patterns...........................................................................74 ed/hd test patterns ..................................................................74 appendix 5sd timing................................................................75 appendix 6hd timing ..............................................................80 appendix 7video output levels...............................................81 sd yprpb output levelssmpte/ebu n10........................81 ed/hd yprpb output levels ...................................................82 sd/ed/hd rgb output levels................................................83 sd output plots ..........................................................................84 appendix 8video standards ......................................................85 outline dimensions........................................................................87 ordering guide ...........................................................................87 revision history 10/06revision 0: initial version
ADV7342/adv7343 rev. 0 | page 4 of 88 detailed features high definition (hd) programmable features (720p/1080i/1035i) 4 oversampling (297 mhz) internal test pattern generator fully programmable ycrcb to rgb matrix gamma correction programmable adaptive filter control programmable sharpness filter control cgms (720p/1080i) and cgms type b (720p/1080i) undershoot limiter dual data rate (ddr) input support eia/cea-861b compliance support enhanced definition(ed) programmable features (525p/625p) 8 oversampling (216 mhz output) internal test pattern generator color and black bar, hatch, flat field/frame individual y and prpb output delay gamma correction programmable adaptive filter control fully programmable ycrcb to rgb matrix undershoot limiter macrovision rev 1.2 (525p/625p) cgms (525p/625p) and cgms type b (525p) dual data rate (ddr) input support eia/cea-861b compliance support standard definition (sd) programmable features 16 oversampling (216 mhz) internal test pattern generator color and black bar controlled edge rates for start and end of active video individual y and prpb output delay undershoot limiter gamma correction digital noise reduction (dnr) multiple chroma and luma filters luma-ssaf? filter with programmable gain/attenuation prpb ssaf? separate pedestal control on component and composite/s-video output vcr ff/rw sync mode macrovision rev 7.1.l1 copy generation management system (cgms) wide screen signaling closed captioning eia/cea-861b compliance support general description the ADV7342/adv7343 are high speed, digital-to-analog video encoders in a 64-lead lqfp package. six high speed, 3.3 v, 11-bit video dacs provide support for composite (cvbs), s- video (y/c), and component (yprpb/rgb) analog outputs in either standard definition (sd), enhanced definition (ed), or high definition (hd) video formats. the ADV7342/adv7343 each have a 24-bit pixel input port that can be configured in a variety of ways. sd video formats are supported over a sdr interface and ed/hd video formats are supported over sdr and ddr interfaces. pixel data can be supplied in either the ycrcb or rgb color spaces. the parts also support embedded eav/sav timing codes, external video synchronization signals, and i 2 c and spi communication protocols. in addition, simultaneous sd and ed/hd input and output are supported. 216 mhz (sd and ed) and 297 mhz (hd) oversampling ensures that external output filtering is not required, while full-drive dacs ensure that external output buffering is not required. cable detection and dac auto power-down features keep power consumption to a minimum. table 1 lists the video standards directly supported by the ADV7342/adv7343. table 1. standards directly supported by the ADV7342/adv7343 1 resolution i/p 2 frame rate (hz) clock input (mhz) standard 720 240 p 59.94 27 720 288 p 50 27 720 480 i 29.97 27 itu-r bt.601/656 720 576 i 25 27 itu-r bt.601/656 720 480 i 29.97 24.54 ntsc square pixel 720 576 i 25 29.5 pal square pixel 720 483 p 59.94 27 smpte 293m 720 483 p 59.94 27 bta t-1004 720 483 p 59.94 27 itu-r bt.1358 720 576 p 50 27 itu-r bt.1358 720 483 p 59.94 27 itu-r bt.1362 720 576 p 50 27 itu-r bt.1362 1920 1035 i 30 74.25 smpte 240m 1920 1035 i 29.97 74.1758 smpte 240m 1280 720 p 60, 50, 30, 25, 24 74.25 smpte 296m 1280 720 p 23.97, 59.94, 29.97 74.1758 smpte 296m 1920 1080 i 30, 25 74.25 smpte 274m 1920 1080 i 29.97 74.1758 smpte 274m 1920 1080 p 30, 25, 24 74.25 smpte 274m 1920 1080 p 23.98, 29.97 74.1758 smpte 274m 1920 1080 p 24 74.25 itu-r bt. 709-5 1 other standards are supported in the ed/hd nonstandard timing mode. 2 i = interlaced, p = progressive.
ADV7342/adv7343 rev. 0 | page 5 of 88 specifications power supply and volt age specifications all specifications t min to t max (?40c to +85c), unless otherwise noted. table 2. parameter conditions min typ max unit supply voltages v dd 1.71 1.8 1.89 v v dd_io 2.97 3.3 3.63 v pv dd 1.71 1.8 1.89 v v aa 2.6 3.3 3.465 v power supply rejection ratio 0.002 %/% voltage reference specifications all specifications t min to t max (?40c to +85c), unless otherwise noted. table 3. parameter conditions min typ max unit internal reference range, v ref 1.186 1.248 1.31 v external reference range, v ref 1.15 1.235 1.31 v external v ref current 1 10 a 1 external current required to overdrive internal v ref . input clock specifications v dd = 1.71 v to 1.89 v. pv dd = 1.71 v to 1.89 v. v aa = 2.6 v to 3.465 v. v dd_io = 2.97 v to 3.63 v. all specifications t min to t max (?40c to +85c), unless otherwise noted. table 4. parameter conditions 1 min typ max unit f clkin_a sd/ed 27 mhz f clkin_a ed (at 54 mhz) 54 mhz f clkin_a hd 74.25 mhz f clkin_b ed 27 mhz f clkin_b hd 74.25 mhz clkin_a high time, t 9 40 % of one clock cycle clkin_a low time, t 10 40 % of one clock cycle clkin_b high time, t 9 40 % of one clock cycle clkin_b low time, t 10 40 % of one clock cycle clkin_a peak-to-peak jitter tolerance 2 ns clkin_b peak-to-peak jitter tolerance 2 ns 1 sd = standard defini tion, ed = enhanced definition (525p/625p), hd = high definition.
ADV7342/adv7343 rev. 0 | page 6 of 88 analog output specifications v dd = 1.71 v to 1.89 v. pv dd = 1.71 v to 1.89 v. v aa = 2.6 v to 3.465 v. v dd_io = 2.97 v to 3.63 v. v ref = 1.235 v (driven externally). all specifications t min to t max (?40c to +85c), unless otherwise noted. table 5. parameter conditions min typ max unit full-drive output current (full-scale) 1 r set = 510 , r l = 37.5 33 34.6 37 ma low drive output current (full-scale) 2 r set = 4.12 k, r l = 300 4.1 4.3 4.5 ma dac-to-dac matching dac 1 to dac 6 1.0 % output compliance, v oc 0 1.4 v output capacitance, c out dac 1, dac 2, dac 3 10 pf dac 4, dac 5, dac 6 6 pf analog output delay 3 dac 1, dac 2, dac 3 8 ns dac 4, dac 5, dac 6 6 ns dac analog output skew dac 1, dac 2, dac 3 2 ns dac 4, dac 5, dac 6 1 ns 1 applicable to full-drive capable dacs only, that is, dac 1, dac 2, dac 3. 2 applicable to all dacs. 3 output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the dac output full-scale t ransition. digital input/output specifications v dd = 1.71 v to 1.89 v. pv dd = 1.71 v to 1.89 v. v aa = 2.6 v to 3.465 v. v dd_io = 2.97 v to 3.63 v. all specifications t min to t max (?40c to +85c), unless otherwise noted. table 6. parameter conditions min typ max unit input high voltage, v ih 2.0 v input low voltage, v il 0.8 v input leakage current, i in v in = v dd_io 10 a input capacitance, c in 4 pf output high voltage, v oh i source = 400 a 2.4 v output low voltage, v ol i sink = 3.2 ma 0.4 v three-state leakage current v in = 0.4 v, 2.4 v 1.0 a three-state output capacitance 4 pf
ADV7342/adv7343 rev. 0 | page 7 of 88 digital timing specifications v dd = 1.71 v to 1.89 v. pv dd = 1.71 v to 1.89 v. v aa = 2.6 v to 3.465 v. v dd_io = 2.97 v to 3.63 v. all specifications t min to t max (?40c to +85c), unless otherwise noted. table 7. parameter conditions 1 min typ max unit video data and video control port 2, 3 data setup time, t 11 4 sd 2.1 ns ed/hd-sdr 2.3 ns ed/hd-ddr 2.3 ns ed (at 54 mhz) 1.7 ns data hold time, t 12 4 sd 1.0 ns ed/hd-sdr 1.1 ns ed/hd-ddr 1.1 ns ed (at 54 mhz) 1.0 ns control setup time, t 11 4 sd 2.1 ns ed/hd-sdr or ed/hd-ddr 2.3 ns ed (at 54 mhz) 1.7 ns control hold time, t 12 4 sd 1.0 ns ed/hd-sdr or ed/hd-ddr 1.1 ns ed (at 54 mhz) 1.0 ns digital output access time, t 13 4 sd 12 ns ed/hd-sdr, ed/hd-ddr or ed (at 54 mhz) 10 ns digital output hold time, t 14 4 sd 4.0 ns ed/hd-sdr, ed/hd-ddr or ed (at 54 mhz) 3.5 ns pipeline delay 5 sd 1 cvbs/yc outputs (2) sd oversampling disabled 68 clock cycles cvbs/yc outputs (16) sd oversampling enabled 67 clock cycles component outputs (2) sd oversamp ling disabled 78 clock cycles component outputs (16) sd oversamp ling enabled 84 clock cycles ed 1 component outputs (1) ed oversamp ling disabled 41 clock cycles component outputs (8) ed oversamp ling enabled 46 clock cycles hd 1 component outputs (1) hd oversamp ling disabled 40 clock cycles component outputs (4) hd oversamp ling enabled 44 clock cycles 1 sd = standard definition, ed = enhanced definition (525p/625p), hd = high definition, sdr = single data rate, ddr = dual data rate. 2 video data: c[7:0], y[7:0], and s[7:0]. 3 video control: p_hsync , p_vsync , p_blank , s_hsync , and s_vsync . 4 guaranteed by characterization. 5 guaranteed by design.
ADV7342/adv7343 rev. 0 | page 8 of 88 mpu port timing specifications v dd = 1.71 v to 1.89 v. pv dd = 1.71 v to 1.89 v. v aa = 2.6 v to 3.465 v. v dd_io = 2.97 v to 3.63 v. all specifications t min to t max (?40c to +85c), unless otherwise noted. table 8. parameter conditions min typ max unit mpu port, i 2 c mode 1 scl frequency 0 400 khz scl high pulse width, t 1 0.6 s scl low pulse width, t 2 1.3 s hold time (start condition), t 3 0.6 s setup time (start condition), t 4 0.6 s data setup time, t 5 100 ns sda, scl rise time, t 6 300 ns sda, scl fall time, t 7 300 ns setup time (stop condition), t 8 see figure 19 0.6 s mpu port, spi mode 1 sclk frequency 0 10 mhz spi_ss to sclk setup time, t 1 20 ns sclk high pulse width, t 2 50 ns sclk low pulse width, t 3 50 ns data access time after sclk falling edge, t 4 35 ns data setup time prior to sclk rising edge, t 5 20 ns data hold time after sclk rising edge, t 6 0 ns spi_ss to sclk hold time, t 7 0 ns spi_ss to miso high impedance, t 8 see figure 20 40 ns 1 guaranteed by characterization. power specifications v dd = 1.8 v, pv dd = 1.8 v, v aa = 3.3 v, v dd_io = 3.3 v, t a = +25c. table 9. parameter conditions min typ max unit normal power mode 1, 2 i dd 3 sd only (16 oversampling) 90 ma ed only (8 oversampling) 4 65 ma hd only (4 oversampling) 4 91 ma sd (16 oversampling) and ed (8 oversampling) 95 ma sd (16 oversampling) and hd (4 oversampling) 122 ma i dd_io 1 ma i aa 3 dacs enabled (ed/hd only) 124 ma 6 dacs enabled (sd only and simultaneous modes ) 140 ma i pll sd only, ed only or hd only modes 5 ma simultaneous modes 10 ma sleep mode i dd 5 a i aa 0.3 a i dd_io 0.2 a i pll 0.1 a 1 r set1 = 510 (dac 1, dac 2, and dac 3 operating in full- drive mode). r set2 = 4.12 k (dac 4, dac 5, and dac 6 operating in low drive mode). 2 75% color bar test pattern applied to pixel data pins. 3 i dd is the continuous current required to drive the digital core. 4 applicable to both single data rate (sdr) and dual da ta rate (ddr) input modes.
ADV7342/adv7343 rev. 0 | page 9 of 88 video performance specifications v dd = 1.8 v, pv dd = 1.8 v, v aa = 3.3 v, v dd_io = 3.3 v, t a = 25c, v ref driven externally. table 10. parameter conditions min typ max unit static performance resolution 11 bits integral nonlinearity r set1 = 510 k, r l1 = 37.5 0.4 lsbs r set2 = 4.12 k, r l2 = 300 0.5 lsbs differential nonlinearity 1 +ve r set1 = 510 k, r l1 = 37.5 0.15 lsbs r set2 = 4.12 k, r l2 = 300 0.5 lsbs differential nonlinearity 1 ?ve r set1 = 510 k, r l1 = 37.5 0.25 lsbs r set2 = 4.12 k, r l2 = 300 0.2 lsbs standard defintion (sd) mode luminance nonlinearity 0.5 % differential gain ntsc 0.5 % differential phase ntsc 0.6 degrees signal-to-noise ratio (snr) luma ramp 58 db flat field full bandwidth 75 db enhanced definition (ed) mode luma bandwidth 12.5 mhz chroma bandwidth 5.8 mhz high definition (hd) mode luma bandwidth 30 mhz chroma bandwidth 13.75 mhz 1 differential nonlinearity (dnl) measures the deviation of the actual dac output voltage step from the ideal. for +ve dnl, the actual step value lies above the ideal step value. for ?ve dnl, the actual step value lies below the ideal step value.
ADV7342/adv7343 rev. 0 | page 10 of 88 timing diagrams the following abbreviations are used in figure 2 to figure 13: ? t 9 = clock high time ? t 10 = clock low time ? t 11 = data setup time ? t 12 = data hold time ? t 13 = control output access time ? t 14 = control output hold time in addition, refer to table 31 for the ADV7342/adv7343 input configuration. t 9 clkin_a t 10 control outputs s_hsync, s_vsync cr2 cb2 cr0 cb0 *selected by subaddress 0x01, bit 7. in master/slave mode in slave mode y0 y1 y2 s7 to s0/ y7 to y0* control inputs t 12 t 11 t 13 t 14 06399-002 figure 2. sd only, 8-bit, 4:2:2 ycrcb pixel input mode (input mode 000) in master/slave mode in slave mode clkin_a control outputs s_hsync, s_vsync *selected by subaddress 0x01, bit 7. s7 to s0/ y7 to y0* y7 to y0/ c7 to c0* control inputs t 9 t 10 cr2 cb2 cr0 cb0 y0 y1 y2 y3 t 12 t 14 t 11 t 13 06399-003 figure 3. sd only, 16-bit, 4:2:2 ycrcb pixel input mode (input mode 000) c7 to c0 y7 to y0 control outputs s7 to s0 t 9 clkin_a t 10 s_hsync, s_vsync control inputs t 11 g0 g1 g2 b0 b1 b2 r0 r1 r2 t 12 t 14 t 13 06399-004 figure 4. sd only, 24-bit, 4:4:4 rgb pixel input mode (input mode 000)
ADV7342/adv7343 rev. 0 | page 11 of 88 y0 y1 y2 y3 y4 y5 y7 to y0 cr4 cb4 cr2 cb2 cr0 cb0 control outputs clkin_a p_hsync, p_vsync, control inputs p_blank c7 to c0 t 9 t 10 t 12 t 11 t 14 t 13 06399-005 figure 5. ed/hd-sdr only, 16-bit, 4:2:2 ycrcb pixel input mode (input mode 001) y0 y1 y2 y3 y4 y5 cr4 cr3 cr2 cr1 cr0 cr5 cb4 cb3 cb2 cb1 cb0 cb5 y7 to y0 control outputs clkin_a p_hsync, p_vsync, control inputs p_blank c7 to c0 s7 to s0 t 9 t 10 t 12 t 11 t 14 t 13 06399-006 figure 6. ed/hd-sdr only, 24-bit, 4:4:4 ycrcb pixel input mode (input mode 001) clkin_a c7 to c0 g0 g1 g2 g3 g4 g5 b0 b1 b2 b3 b4 b5 r0 r1 r2 r3 r4 r5 y7 to y0 control outputs s7 to s0 p_hsync, p_vsync, c ontrol inputs p_blank t 9 t 10 t 12 t 11 t 14 t 13 06399-007 figure 7. ed/hd-sdr only, 24-bit, 4:4:4 rgb pixel input mode (input mode 001)
ADV7342/adv7343 rev. 0 | page 12 of 88 clkin_a* y7 to y0 *luma/chroma clock relationship can be inverted using subaddress 0x01, bits 1 and 2. control outputs cr2 y2 cb2 y1 cr0 y0 cb0 t 9 t 10 t 12 t 11 t 12 t 11 t 14 t 13 p_hsync, p_vsync, control inputs p_blank 06399-008 figure 8. ed/hd-ddr only, 8-bit, 4:2:2 ycrcb ( hsync / vsync ) pixel input mode (input mode 010) y1 cr0 y0 cb0 xy 00 00 3ff *luma/chroma clock relationship can be inverted using subaddress 0x01, bits 1 and 2. clkin_a* y7 to y0 control outputs t 9 t 10 t 12 t 11 t 12 t 11 t 14 t 13 06399-009 figure 9. ed/hd-ddr only, 8-bit, 4:2:2 ycrcb (eav/sav) pixel input mode (input mode 010) t 9 t 10 t 9 t 10 t 11 t 11 y0 y1 y2 y3 y4 y5 ed/hd input sd input s7 to s0 clkin_a y2 cb2 y1 cr0 y0 cb0 cr4 cb4 cr2 cb2 cr0 cb0 cr2 y6 cb6 c7 to c0 y7 to y0 clkin_b p_hsync, p_vsync, control inputs p_blank s_hsync, s_vsync control inputs t 12 t 12 06399-010 figure 10. sd and ed/hd-sdr, 16-bit, 4:2:2 ed/hd and 8-bit, sd pixel input mode (input mode 011)
ADV7342/adv7343 rev. 0 | page 13 of 88 cr2 cr2 y2 y1 cr0 eh/hd input sd input cb2 y1 cr0 s7 to s0 clkin_a y7 to y0 clkin_b p_hsync, p_vsync, control inputs p_blank s_hsync, s_vsync control inputs t 9 t 10 t 9 t 10 t 12 t 11 t 12 t 11 t 12 t 11 y0 cb0 cb2 cb0 y0 y2 06399-011 figure 11. sd and ed/hd-ddr, 8-bit, 4:2:2 ed/hd an d 8-bit, sd pixel input mode (input mode 100) clkin_a y7 to y0 control outputs y1 cr0 y0 cb0 cr2 y2 cb2 p_hsync, p_vsync, control inputs p_blank t 9 t 10 t 12 t 11 t 13 t 14 06399-012 figure 12. ed only (at 54 mhz), 8-bit, 4:2:2 ycrcb ( hsync / vsync ) pixel input mode (input mode 111) t 9 t 11 t 10 t 12 t 13 t 14 clkin_a y7 to y0 control outputs 3ff 00 00 xy cb0 y0 cr0 y1 06399-013 figure 13. ed only (at 54 mhz), 8-bit, 4:2:2 ycrcb (eav/sav) pixel input mode (input mode 111)
ADV7342/adv7343 rev. 0 | page 14 of 88 y0 y1 y2 y3 b a cr2 cb2 cr0 cb0 c y output p_hsync p_vsync p_blank y7 to y0 c7 to c0 a and b as per relevant standard. c = pipeline delay. please refer to relevant pipeline delay. this can be found in the digital timin g specification section of the data sheet. a falling edge of hsync into the encoder generates a sync falling edge on the output after a time equal to the pipeline delay. 06399-014 figure 14. ed-sdr, 16-bit, 4:2:2 ycrcb ( hsync / vsync ) input timing diagram y7 to y0 cb0 y0 cr0 y1 b a a = 32 clock cycles for 525p a = 24 clock cycles for 625p as recommended by standard b(min) = 244 clock cycles for 525p b(min) = 264 clock cycles for 625p p_hsyn c p_vsync p_blank c y output c = pipeline delay. please refer to relevant pipeline delay. this can be found in the digital timing specification section of the data sheet. a falling edge of hsync into the encoder generates a sync falling edge on the output after a time equal to the pipeline delay. 0 6399-015 figure 15. ed-ddr, 8-bit, 4:2:2 ycrcb ( hsync / vsync ) input timing diagram
ADV7342/adv7343 rev. 0 | page 15 of 88 y0 y1 y2 y3 b a cr2 cb2 cr0 cb0 c y output p_hsync p_vsync p_blank y7 to y0 c7 to c0 a and b as per relevant standard. c = pipeline delay. please refer to relevant pipeline delay. this can be found in the digital timin g specification section of the data sheet. a falling edge of hsync into the encoder generates a falling edge of tri-level sync on the output a fter a time equal to the pipeline delay. 06399-016 figure 16. hd-sdr, 16-bit, 4:2:2 ycrcb ( hsync / vsync ) input timing diagram y7 to y0 cb0 y0 cr0 y1 b a p_hsync p_vsync p_blank c y output a and b as per relevant standard. c = pipeline delay. please refer to relevant pipeline delay. this can be found in the digital timing specification section of the data sheet. a falling edge of hsync into the encoder generates a falling edge of tri-level sync on the output after a time equal to the pipeline delay. 06399-017 figure 17. hd-ddr, 8-bit, 4:2:2 ycrcb ( hsync / vsync ) input timing diagram
ADV7342/adv7343 rev. 0 | page 16 of 88 cb y cr y pal = 264 clock cycles ntsc = 244 clock cycles y7 to y0* s_vsync s_hsync *selected by subaddress 0x01, bit 7. 0 6399-018 figure 18. sd input timing diagram (timing mode 1) t 3 t 3 t 4 t 7 t 8 t 5 sda scl t 1 t 2 t 6 06399-019 figure 19. mpu port timing diagram (i 2 c mode) spi_ss sclk mosi miso x xx x x x x x x x d7d6d5d4d3d2d1d0 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx t 1 t 2 t 3 t 5 t 6 t 4 t 8 t 7 06399-020 figure 20. mpu port timing diagram (spi mode)
ADV7342/adv7343 rev. 0 | page 17 of 88 absolute maximum ratings table 11. parameter 1 rating v aa to agnd ?0.3 v to +3.9 v v dd to dgnd ?0.3 v to +2.3 v pv dd to pgnd ?0.3 v to +2.3 v v dd_io to gnd_io ?0.3 v to +3.9 v v aa to v dd ?0.3 v to +2.2 v v dd to pv dd ?0.3 v to +0.3 v v dd_io to v dd ?0.3 v to +2.2 v agnd to dgnd ?0.3 v to +0.3 v agnd to pgnd ?0.3 v to +0.3 v agnd to gnd_io ?0.3 v to +0.3 v dgnd to pgnd ?0.3 v to +0.3 v dgnd to gnd_io ?0.3 v to +0.3 v pgnd to gnd_io ?0.3 v to +0.3 v digital input voltage to gnd_io ?0.3 v to v dd_io + 0.3 v analog outputs to agnd ?0.3 v to v aa storage temperature range (t s ) ?65c to +150c junction temperature (t j ) 150c lead temperature (soldering, 10 sec) 260c 1 analog output short circuit to any power supply or common can be of an indefinite duration. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. the ADV7342/adv7343 are high performance integrated circuits with an esd rating of <1 kv, and it is esd sensitive. proper precautions should be taken for handling and assembly. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 12. thermal resistance 1 package type ja jc unit 64-lead lqfp 47 11 c/w 1 values are based on a jedec 4 layer test board. the ADV7342/adv7343 are pb-free products. the lead finish is 100% pure sn electroplate. the devices are rohs compliant, suitable for pb-free applications up to 255c (5c) ir reflow (jedec std-20). they are backward-compatible with conventional snpb soldering processes. the electroplated sn coating can be soldered with sn/pb solder paste at conventional reflow temperatures of 220c to 235c. esd caution
ADV7342/adv7343 rev. 0 | page 18 of 88 pin configuration and fu nction descriptions 64 gnd_io 63 clkin_b 62 s7 61 s6 60 s5 59 s4 58 s3 57 dgnd 56 v dd 55 s2 54 s1 53 s0 52 test5 51 test4 50 s_hsync 49 s_vsync 47 r set1 46 v ref 45 comp1 42 dac 3 43 dac 2 44 dac 1 48 sfl/miso 41 v aa 40 agnd 39 dac 4 37 dac 6 36 r set2 35 comp2 34 pv dd 33 ext_lf1 38 dac 5 2 test0 3 test1 4 y0 7 y3 6 y2 5 y1 1 v dd_io 8 y4 9 y5 10 v dd 12 y6 13 y7 14 test2 15 test3 16 c0 11 dgnd 17 c1 18 c2 19 alsb/spi_ss 20 sda/sclk 21 scl/mosi 22 23 p_hsync 24 p_vsync 25 p_blank 26 c4 c3 27 c5 28 c6 29 c7 30 clkin_a 31 32 pgnd pin 1 ADV7342/adv7343 top view (not to scale) ext_lf2 06399-021 figure 21. pin configuration table 13. pin function descriptions pin no. mnemonic input/ output description 13, 12, 9 to 4 y7 to y0 i 8-bit pixel port. y0 is the lsb. refer to table 31 for input modes. 29 to 25, 18 to 16 c7 to c0 i 8-bit pixel port. c0 is the lsb. refer to table 31 for input modes. 62 to 58, 55 to 53 s7 to s0 i 8-bit pixel port. s0 is the lsb. refer to table 31 for input modes. 52, 51, 15, 14, 3, 2 test5 to test0 i unused. these pins should be connected to dgnd. 30 clkin_a i pixel clock input for hd only (74.25 mhz), ed 1 only (27 mhz or 54 mhz) or sd only (27 mhz). 63 clkin_b i pixel clock input for dual modes only. requires a 27 mhz reference clock for ed operation or a 74.25 mhz reference clock for hd operation. 50 s_hsync i/o sd horizontal synchronization signal. this pin can also be configured to output an sd, ed, or hd horizontal synchronization signal. see the external horizontal and vertical synchronization control section. 49 s_vsync i/o sd vertical synchronization signal. this pin can a lso be configured to output an sd, ed, or hd vertical synchronization signal. see the external horizontal and vertical synchronization control section. 22 p_hsync i ed/hd horizontal synchronization signal. s ee the external horizontal and vertical synchronization control section. 23 p_vsync i ed/hd vertical synchronization signal. see the external horizontal and vertical synchronization control section. 24 p_blank i ed/hd blanking signal. see the external horizontal and vertical synchronization control section. 48 sfl/miso i/o multifunctional pin: subcarrier frequency lock (sfl) input/spi data output. the sfl input is used to drive the color subcarrier dds sy stem, timing reset, or subcarrier reset. 47 r set1 i this pin is used to control the amplitudes of the dac 1, dac 2, and dac 3 outputs. for full-drive operation (for example, into a 37.5 load), a 510 resistor must be connected from r set1 to agnd. for low drive operation (for example, into a 300 load), a 4.12 k resistor must be connected from r set1 to agnd.
ADV7342/adv7343 rev. 0 | page 19 of 88 pin no. mnemonic input/ output description 36 r set2 i this pin is used to control the amplitudes of the dac 4, dac 5, and dac 6 outputs. a 4.12 k resistor must be connected from r set2 to agnd. 45, 35 comp1, comp2 o compensation pins. connect a 2.2 nf capacitor from both comp pins to v aa . 44, 43, 42 dac 1, dac 2, dac 3 o dac outputs. full and low drive capable dacs. 39, 38, 37 dac 4, dac 5, dac 6 o dac outputs. low drive only capable dacs. 21 scl/mosi i multifunctional pin: i 2 c clock input/spi data input. 20 sda/sclk i/o multifunctional pin: i 2 c data input/output. also, spi clock input. 19 alsb/spi_ss i multifunctional pin: this signal sets up the lsb 2 of the mpu i 2 c address. also, spi slave select. 46 v ref optional external voltage reference input for dacs or voltage reference output. 41 v aa p analog power supply (3.3 v). 10, 56 v dd p digital power supply (1.8 v). for dual-supply configurations, v dd can be connected to other 1.8 v supplies through a ferrite bead or suitable filtering. 1 v dd_io p input/output digital power supply (3.3 v). 34 pv dd p pll power supply (1.8 v). for dual-supply configurations, pv dd can be connected to other 1.8 v supplies through a ferrite bead or suitable filtering. 33 ext_lf1 i external loop filter for on-chip pll 1. 31 ext_lf2 i external loop filter for on-chip pll 2. 32 pgnd g pll ground pin. 40 agnd g analog ground pin. 11, 57 dgnd g digital ground pin. 64 gnd_io g input/output supply ground pin. 1 ed = enhanced definition = 525p and 625p. 2 lsb = least significant bi t. in the ADV7342, setting the lsb to 0 sets the i 2 c address to 0xd4. setting it to 1 sets the i 2 c address to 0xd6. in the adv7343, setting the lsb to 0 sets the i 2 c address to 0x54. setting it to 1 sets the i 2 c address to 0x56.
ADV7342/adv7343 rev. 0 | page 20 of 88 typical performance characteristics frequency (mhz) edpr/pb response. linear interp from 4:2:2 to 4:4:4 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 200 20 40 60 80 100 120 140 160 180 0 06399-022 figure 22. ed 8 oversampling, prpb filter (linear) response frequency (mhz) ed pr/pb response. ssaf interp from 4:2:2 to 4:4:4 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 200 20 40 60 80 100 120 140 160 180 0 06399-023 figure 23. ed 8 oversampling, prpb filter (ssaf) response frequency (mhz) y response in ed 8 oversampling mode 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 200 20 40 60 80 100 120 140 160 180 0 06399-024 figure 24. ed 8 oversampling, y filter response frequency (mhz) y response in ed 8 oversampling mode gain (db) ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 ?3.0 12 246810 0 06399-025 figure 25. ed 8 oversampling, y filter response (focus on pass band) frequency (mhz) hd pr/pb response. ssaf interp from 4:2:2 to 4:4:4 10 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?100 ?80 ?90 148.0 18.5 37.0 55.5 74.0 92.5 111.0 129.5 0 06399-026 figure 26. hd 4 oversampling, prpb (ssaf) filter response (4:2:2 input) hd pr/pb response. 4:4:4 input mode gain (db) frequency (mhz) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 20 30 40 50 60 70 80 90 100 110 120 130 140 0 6399-027 figure 27. hd 4 oversampling, prpb (ssaf) filter response (4:4:4 input)
ADV7342/adv7343 rev. 0 | page 21 of 88 frequency (mhz) y response in hd 4 oversampling mode 10 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?100 ?80 ?90 148.0 18.5 37.0 55.5 74.0 92.5 111.0 129.5 0 06399-028 figure 28. hd 4 oversampling, y filter response y pass band in hd 4x oversampling mode 3.0 ?12.0 27.750 46.250 frequency (mhz) gain (db) 1.5 0 ?1.5 ?3.0 ?4.5 ?6.0 ?7.5 ?9.0 ?10.5 30.063 32.375 34.688 37.000 39.312 41.625 43.937 06399-029 figure 29. hd 4 oversampling, y filter response (focus on pass band) frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 0 6399-030 figure 30. sd ntsc, luma low-pass filter response frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 0 6399-031 figure 31. sd pal, luma low-pass filter response frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 06399-032 figure 32. sd ntsc, luma notch filter response frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 06399-033 figure 33. sd pal, luma notch filter response
ADV7342/adv7343 rev. 0 | page 22 of 88 frequency (mhz) y response in sd oversampling mode gain (db) 0 ?50 ?80 0 20 40 60 80 100 120 140 160 180 200 ?10 ?40 ?60 ?70 ?20 ?30 06399-034 figure 34. sd, 16 oversampling, y filter response frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 06399-035 figure 35. sd luma ssaf filter response up to 12 mhz frequency (mhz) 4 7 magnitude (db) 2 ?2 ?6 ?8 ?12 0 ?4 5 ?10 6 0 1 234 06399-036 figure 36. sd luma ssaf filter, programmable responses frequency (mhz) 7 magnitude (db) 5 4 2 1 ?1 3 5 0 6 0 1 234 06399-037 figure 37. sd luma ssaf fi lter, programmable gain frequency (mhz) 7 magnitude (db) 1 0 ?2 ?3 ?5 ?1 5 ?4 6 0 1 234 0 6399-038 figure 38. sd luma ssaf filter, programmable attenuation frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 06399-039 figure 39. sd luma cif low-pass filter response
ADV7342/adv7343 rev. 0 | page 23 of 88 frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 06399-040 figure 40. sd luma qcif low-pass filter response frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 06399-041 figure 41. sd chroma 3.0 mhz low-pass filter response frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 06399-042 figure 42. sd chroma 2.0 mhz low-pass filter response frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 06399-043 figure 43. sd chroma 1.3 mhz low-pass filter response frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 0 6399-044 figure 44. sd chroma 1.0 mhz low-pass filter response frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 06399-045 figure 45. sd chroma 0.65 mhz low-pass filter response
ADV7342/adv7343 rev. 0 | page 24 of 88 frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 0 6399-046 figure 46. sd chroma cif low-pass filter response frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 06399-047 figure 47. sd chroma qcif low-pass filter response
ADV7342/adv7343 rev. 0 | page 25 of 88 mpu port description devices such as a microprocessor can communicate with the ADV7342/adv7343 through one of the following protocols: ? 2-wire serial (i 2 c-compatible) bus ? 4-wire serial (spi-compatible) bus after power-up or reset, the mpu port is configured for i 2 c operation. spi operation can be invoked at any time by following the procedure outlined in the spi operation section. i 2 c operation the ADV7342/adv7343 support a 2-wire serial (i 2 c-compatible) microprocessor bus driving multiple peripherals. this port operates in an open-drain configuration. two inputs, serial data (sda) and serial clock (scl), carry information between any device connected to the bus and the ADV7342/adv7343. each slave device is recognized by a unique address. the ADV7342/ adv7343 have four possible slave addresses for both read and write operations. these are unique addresses for each device and are illustrated in figure 48. the lsb either sets a read or write operation. logic 1 corresponds to a read operation, while logic 0 corresponds to a write operation. a1 is controlled by setting the alsb/ spi_ss pin of the ADV7342/adv7343 to logic 0 or logic 1. 1 1 0 1 0 1 a1 x address control set up by alsb/spi_ss read/write control 0 write 1 read 06399-048 figure 48. ADV7342 slave address = 0xd4 or 0xd6 to control the various devices on the bus, use the following protocol. the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on sda while scl remains high. this indicates that an address/data stream follows. all peripherals respond to the start condition and shift the next eight bits (7-bit address + r/ w bit). the bits are transferred from msb down to lsb. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowledge bit. all other devices withdraw from the bus at this point and maintain an idle condition. the idle condition occurs when the device monitors the sda and scl lines waiting for the start condition and the correct transmitted address. the r/ w bit determines the direction of the data. logic 0 on the lsb of the first byte means that the master writes information to the peripheral. logic 1 on the lsb of the first byte means that the master reads information from the peripheral. the ADV7342/adv7343 act as a standard slave device on the bus. the data on the sda pin is eight bits long, supporting the 7-bit addresses plus the r/ w bit. it interprets the first byte as the device address and the second byte as the starting subaddress. there is a subaddress auto-increment facility. this allows data to be written to or read from registers in ascending subaddress sequence starting at any valid subaddress. a data transfer is always terminated by a stop condition. the user can also access any unique subaddress register on a one-by-one basis without updating all the registers. stop and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. during a given scl high period, the user should issue only a start condition, a stop condition, or a stop condition followed by a start condition. if an invalid subaddress is issued by the user, the ADV7342/adv7343 do not issue an acknowledge and do return to the idle condition. if the user utilizes the auto-increment method of addressing the encoder and exceeds the highest subaddress, the following actions are taken: ? in read mode, the highest subaddress register contents are output until the master device issues a no acknowledge. this indicates the end of a read. a no acknowledge condition occurs when the sda line is not pulled low on the ninth pulse. ? in write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the ADV7342/adv7343, and the parts return to the idle condition.
ADV7342/adv7343 rev. 0 | page 26 of 88 figure 49 shows an example of data transfer for a write sequence and the start and stop conditions. figure 50 shows bus write a nd read sequences. sda scl start addr r/w ack subaddress ack data ack stop 1?7 8 9 s 1?7 1?7 p 8 9 8 9 06399-049 figure 49. i 2 c data transfer write sequence read sequence s slave addr a(s) subaddr a(s) data data a(s) p s slave addr a(s) subaddr a(s) s slave addr a(s) data data a(m) a(m) p s = start bit p = stop bit a(s) = acknowledge by slave a(m) = acknowledge by master a (s) = no-acknowledge by slave a (m) = no-acknowledge by master lsb = 0 lsb = 1 a(s) 06399-050 figure 50. i 2 c read and write sequence spi operation the ADV7342/adv7343 support a 4-wire serial (spi-compatible) bus connecting multiple peripherals. two inputs, master out slave in (mosi) and serial clock (sclk), and one output, master in slave out (miso), carry information between a master spi peripheral on the bus and the ADV7342/adv7343. each slave device on the bus has a slave select pin that is connected to the master spi peripheral by a unique slave select line. as such, slave device addressing is not required. to invoke spi operation, a master spi peripheral (for example, a microprocessor) should issue three low pulses on the ADV7342/ adv7343 alsb/ spi_ss pin. when the encoder detects the third rising edge on the alsb/ spi_ss pin, it automatically switches to spi communication mode. the ADV7342/adv7343 remain in spi communication mode until a reset or power- down occurs. to control the ADV7342/adv7343, use the following protocol for both read and write transactions. first, the master initiates a data transfer by driving and holding the ADV7342/adv7343 alsb/ spi_ss pin low. on the first sclk rising edge after alsb/ spi_ss has been driven low, the write command, defined as 0xd4, is written to the ADV7342/adv7343 over the mosi line. the second byte written to the mosi line is interpreted as the starting subaddress. data on the mosi line is written msb first and clocked on the rising edge of sclk. there is a subaddress auto-increment facility. this allows data to be written to or read from registers in ascending subaddress sequence starting at any valid subaddress. the user can also access any unique subaddress register on a one-by-one basis. in a write data transfer, 8-bit data bytes are written to the ADV7342/adv7343, msb first, on the mosi line immediately after the starting subaddress. the data bytes are clocked into the ADV7342/adv7343 on the rising edge of sclk. when all data bytes have been written, the master completes the transfer by driving and holding the alsb/ spi_ss pin high. in a read data transfer, after the subaddress has been clocked in on the mosi line, the alsb/ spi_ss pin is driven and held high for at least one clock cycle. then, the alsb/ spi_ss pin is driven and held low again. on the first sclk rising edge after alsb/ spi_ss has been driven low, the read command, defined as 0xd5, is written, msb first, to the ADV7342/adv7343 over the mosi line. subsequently, 8-bit data bytes are read from the ADV7342/adv7343, msb first, on the miso line. the data bytes are clocked out of the ADV7342/adv7343 on the falling edge of sclk. when all data bytes have been read, the master completes the transfer by driving and holding the alsb/ spi_ss pin high.
ADV7342/adv7343 rev. 0 | page 27 of 88 register map access a microprocessor can read from or write to all registers of the ADV7342/adv7343 via the mpu port, except for registers that are specified as read-only or write-only registers. the subaddress register determines which register the next read or write operation accesses. all communication through the mpu port starts with an access to the subaddress register. a read/write operation is then performed from/to the target address, which increments to the next address until the transaction is complete. register programming table 14 to table 28 describe the functionality of each register. all registers can be read from as well as written to, unless otherwise stated. subaddress register (sr7 to sr0) the subaddress register is an 8-bit write-only register. after the mpu port is accessed and a read/write operation is selected, the subaddress is set up. the subaddress register determines to or from which register the operation takes place. table 14. register 0x00 sr7 to bit number register reset sr0 register bit description 7 6 5 4 3 2 1 0 setting value 0 sleep mode off. 0x12 sleep mode. with this control enabled, the current consumption is reduced to a level. all dacs and the internal pll circuit are disabled. i 2 c registers can be read from and written to in sleep mode. 1 sleep mode on. 0 pll on. pll and oversampling control. this control allows the internal pll circuit to be powered down and the oversampling to be switched off. 1 pll off. 0 dac 3 off. dac 3: power on/off. 1 dac 3 on. 0 dac 2 off. dac 2: power on/off. 1 dac 2 on. 0 dac 1 off. dac 1: power on/off. 1 dac 1 on. 0 dac 6 off. dac 6: power on/off. 1 dac 6 on. 0 dac 5 off. dac 5: power on/off. 1 dac 5 on. 0 dac 4 off. 0x00 power mode register dac 4: power on/off. 1 dac 4 on.
ADV7342/adv7343 rev. 0 | page 28 of 88 table 15. register 0x01 to register 0x09 sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value reserved. 0 0x00 0 0 chroma clocked in on rising clock edge; luma clocked in on falling clock edge. 0 1 reserved. 1 0 reserved. ddr clock edge alignment. note: only used for ed 1 and hd ddr modes. 1 1 luma clocked in on rising clock edge; chroma clocked in on falling clock edge. reserved. 0 0 0 0 sd input only. 0 0 1 ed/hd-sdr input only. 0 1 0 ed/hd-ddr input only. 0 1 1 sd and ed/hd-sdr. 1 0 0 sd and ed/hd-ddr. 1 0 1 reserved. 1 1 0 reserved. input mode. note: see reg. 0x30, bits[7:3] for ed/hd format selection. 1 1 1 ed only (at 54 mhz). 0 0x01 mode select register y/c/s bus swap. 1 allows data to be applied to data ports in various configurations (sd feature only). reserved. 0 0 0 must be written to these bits. 0x20 0 disabled. test pattern black bar. 2 1 enabled. 0 disable manual csc matrix adjust. manual csc matrix adjust. 1 enable manual csc matrix adjust. 0 no sync. sync on rgb. 1 sync on all rgb outputs. 0 rgb component outputs. rgb/yprpb output select. 1 yprpb component outputs. 0 no sync output. sd sync output enable. 1 output sd syncs on s_hsync and s_vsync pins. 0 no sync output. 0x02 mode register 0 ed/hd sync output enable. 1 output ed/hd syncs on s_hsync and s_vsync pins. 0x03 ed/hd csc matrix 0 x x lsbs for gy. 0x03 x x lsbs for rv. 0xf0 x x lsbs for bu. x x lsbs for gv. 0x04 ed/hd csc matrix 1 x x lsbs for gu. 0x05 ed/hd csc matrix 2 x x x x x x x x bits[9:2 ] for gy. 0x4e 0x06 ed/hd csc matrix 3 x x x x x x x x bits[9:2] for gu. 0x0e 0x07 ed/hd csc matrix 4 x x x x x x x x bits[9:2] for gv. 0x24 0x08 ed/hd csc matrix 5 x x x x x x x x bits[9:2] for bu. 0x92 0x09 ed/hd csc matrix 6 x x x x x x x x bits[9:2] for rv. 0x7c 1 ed = enhanced definition = 525p and 625p. 2 subaddress 0x31, bit 2 must also be enabled (ed/hd). subaddress 0x84, bit 6 must also be enabled (sd).
ADV7342/adv7343 rev. 0 | page 29 of 88 table 16. register 0x0a to register 0x10 sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0 0 0 0 0 0 0 0 0% 0x00 0 0 0 0 0 0 0 1 +0.018% 0 0 0 0 0 0 1 0 +0.036% 0 0 1 1 1 1 1 1 +7.382% positive gain to dac output voltage. 0 1 0 0 0 0 0 0 +7.5% 1 1 0 0 0 0 0 0 ?7.5% 1 1 0 0 0 0 0 1 ?7.382% 1 0 0 0 0 0 1 0 ?7.364% 0x0a dac 4, dac 5, dac 6 output levels negative gain to dac output voltage. 1 1 1 1 1 1 1 1 ?0.018% 0 0 0 0 0 0 0 0 0% 0x00 0 0 0 0 0 0 0 1 +0.018% 0 0 0 0 0 0 1 0 +0.036% 0 0 1 1 1 1 1 1 +7.382% positive gain to dac output voltage. 0 1 0 0 0 0 0 0 +7.5% 1 1 0 0 0 0 0 0 ?7.5% 1 1 0 0 0 0 0 1 ?7.382% 1 0 0 0 0 0 1 0 ?7.364% 0x0b dac 1, dac 2, dac 3 output levels negative gain to dac output voltage. 1 1 1 1 1 1 1 1 ?0.018% 0 dac 1 low power disabled 0x00 dac 1 low power enable. 1 dac 1 low power enabled 0 dac 2 low power disabled dac 2 low power enable. 1 dac 2 low power enabled 0 dac 3 low power disabled dac 3 low power enable. 1 dac 3 low power enabled 0x0d dac power mode reserved. 0 0 0 0 0 0 cable detected on dac 1 0x00 dac 1 cable detect (read only). 1 dac 1 unconnected 0 cable detected on dac 2 dac 2 cable detect (read only). 1 dac 2 unconnected reserved. 0 0 0 dac auto power- down disable unconnected dac auto power-down. 1 dac auto power- down enable 0x10 cable detection reserved. 0 0 0
ADV7342/adv7343 rev. 0 | page 30 of 88 table 17. register 0x12 to register 0x17 sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0x12 pixel port readback (s bus) s[7:0] readback. x x x x x x x x read only 0xxx 0x13 pixel port readback (y bus) y[7: 0] readback. x x x x x x x x read only 0xxx 0x14 pixel port readback (c bus) c[7: 0] readback. x x x x x x x x read only 0xxx p_blank . x 0xxx p_vsync . x p_hsync . x s_vsync . x s_hsync . x sfl/miso. x 0x16 control port readback reserved. 0 0 read only reserved. 0 0x00 0 software reset. 1 writing a 1 resets the device; this is a self-clearing bit 0x17 software reset reserved. 0 0 0 0 0 0
ADV7342/adv7343 rev. 0 | page 31 of 88 table 18. register 0x30 sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting note value 0 0 eia770.2 output. eia770.3 output. ed hd 0x00 0 1 eia770.1 output 1 0 output levels for full input range. ed/hd output standard. 1 1 reserved. 0 external hsync , vsync and field inputs. 1 ed/hd input synchronization format. 1 embedded eav/sav codes. 0 0 0 0 0 smpte 293m, itu-bt.1358. 525p @ 59.94 hz 0 0 0 0 1 nonstandard timing mode. 0 0 0 1 0 bta-1004, itu-bt.1362. 525p @ 59.94 hz 0 0 0 1 1 itu-bt.1358. 625p @ 50 hz 0 0 1 0 0 itu-bt.1362. 625p @ 50 hz 0 0 1 0 1 smpte 296m-1, smpte 274m-2. 720p @ 60/59.94 hz 0 0 1 1 0 smpte 296m-3. 720p @ 50 hz 0 0 1 1 1 smpte 296m-4, smpte 274m-5. 720p @ 30/29.97 hz 0 1 0 0 0 smpte 296m-6. 720p @ 25 hz 0 1 0 0 1 smpte 296m-7, smpte 296m-8. 720p @ 24/23.98 hz 0 1 0 1 0 smpte 240m. 1035i @ 60/59.94 hz 0 1 0 1 1 reserved. 0 1 1 0 0 reserved. 0 1 1 0 1 smpte 274m-4, smpte 274m-5. 1080i @ 30/29.97 hz 0 1 1 1 0 smpte 274m-6. 1080i @ 25 hz 0 1 1 1 1 smpte 274m-7, smpte 274m-8. 1080p @ 0/29.97 hz 1 0 0 0 0 smpte 274m-9. 1080p @ 25 hz 1 0 0 0 1 smpte 274m-10, smpte 274m-11. 1080p @ 4/23.98 hz 1 0 0 1 0 itu-r bt.709-5. 1080psf @ 24 hz 0x30 ed/hd mode register 1 ed/hd input mode. 10011C11111 reserved. 1 synchronization can be controlle d with a combination of either hsync and vsync inputs or hsync and field inputs, depending on subaddress 0x34, bit 6.
ADV7342/adv7343 rev. 0 | page 32 of 88 table 19. register 0x31 to register 0x33 sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0 pixel data valid off. 0x00 ed/hd pixel data valid. 1 pixel data valid on. reserved. 0 0 ed/hd test pattern off. ed/hd test pattern enable. 1 ed/hd test pattern on. 0 hatch. ed/hd test pattern hatch/field. 1 field/frame. 0 disabled. ed/hd vbi open. 1 enabled. 0 0 disabled. 0 1 ?11 ire 1 0 ?6 ire ed/hd undershoot limiter. 1 1 ?1.5 ire 0 disabled. 0x31 ed/hd mode register 2 ed/hd sharpness filter. 1 enabled. 0 0 0 0 clock cycles. 0x00 0 0 1 1 clock cycle. 0 1 0 2 clock cycles. 0 1 1 3 clock cycles. ed/hd y delay with respect to falling edge of hsync . 1 0 0 4 clock cycles. 0 0 0 0 clock cycles. 0 0 1 1 clock cycle. 0 1 0 2 clock cycles. 0 1 1 3 clock cycles. ed/hd color delay with respect to falling edge of hsync . 1 0 0 4 clock cycles. 0 disabled. ed/hd cgms. 1 enabled. 0 disabled. 0x32 ed/hd mode register 3 ed/hd cgms crc. 1 enabled. 0 cb after falling edge of hsync . 0x68 ed/hd cr/cb sequence. 1 cr after falling edge of hsync . reserved. 0 0 0 must be written to these bits. 0 disabled. sinc compensation filter on dac 1, dac 2, dac 3. 1 enabled. reserved. 0 0 must be written to this bit. 0 disabled. ed/hd chroma ssaf. 1 enabled. 0 4:4:4 ed/hd chroma input. 1 4:2:2 0 disabled. 0x33 ed/hd mode register 4 ed/hd double buffering. 1 enabled.
ADV7342/adv7343 rev. 0 | page 33 of 88 table 20. register 0x34 to register 0x35 sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0 internal ed/hd timing counters enabled. 0x48 ed/hd timing reset. 1 resets the internal ed/hd timing counters. 0 ed/hd hsync control. 1 1 hsync output control (refer to table 51 ). 0 ed/hd vsync control. 1 1 vsync output control (refer to table 52 ). 0 p_blank active high. ed/hd blank polarity. 1 p_blank active low. 0 macrovision disabled. ed macrovision enable. 1 macrovision enabled. reserved. 0 0 must be written to this bit. 0 0 = field input. ed/hd vsync /field input. 1 1 = vsync input. 0 update field/line counter. 0x34 ed/hd mode register 5 horizontal/vertical counters. 2 1 field/line counter free running. reserved. 0 0x00 0 disabled. ed/hd rgb input enable. 1 enabled. 0 disabled. ed/hd sync on prpb. 1 enabled. 0 dac 2 = pb, dac 3 = pr. ed/hd color dac swap. 1 dac 2 = pr, dac 3 = pb. 0 gamma correction curve a. ed/hd gamma correction curve select. 1 gamma correction curve b. 0 disabled. ed/hd gamma correction enable. 1 enabled. 0 mode a. ed/hd adaptive filter mode. 1 mode b. 0 disabled. 0x35 ed/hd mode register 6 ed/hd adaptive filter enable 1 enabled. 1 used in conjunction with ed/hd sync in subaddress 0x02, bit 7, set to 1. 2 when set to 0, the horizontal/vertical counters automatically wr ap around at the end of the line/field/frame of the selected s tandard. when set to 1, the horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
ADV7342/adv7343 rev. 0 | page 34 of 88 table 21. register 0x36 to register 0x43 sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0x36 ed/hd y level 1 ed/hd test pattern y level. x x x x x x x x y level value 0xa0 0x37 ed/hd cr level 1 ed/hd test pattern cr level. x x x x x x x x cr level value 0x80 0x38 ed/hd cb level 1 ed/hd test pattern cb level. x x x x x x x x cb level value 0x80 reserved. 0 0 0 0 0 0 disabled ed/hd eia/cea-861b synchronization compliance. 1 enabled 0x39 ed/hd mode register 7 reserved. 0 0 0 0 0 0 gain a = 0 0x00 0 0 0 1 gain a = +1 0 1 1 1 gain a = +7 1 0 0 0 gain a = ?8 ed/hd sharpness filter gain, value a. 1 1 1 1 gain a = ?1 0 0 0 0 gain b = 0 0 0 0 1 gain b = +1 0 1 1 1 gain b = +7 1 0 0 0 gain b = ?8 0x40 ed/hd sharpness filter gain ed/hd sharpness filter gain, value b. 1 1 1 1 gain b = ?1 0x41 ed/hd cgms data 0 ed/hd cgms data bits. 0 0 0 0 c19 c18 c17 c16 cgms c19 to c16 0x00 0x42 ed/hd cgms data 1 ed/hd cgms data bits. c15 c14 c13 c12 c11 c10 c9 c8 cgms c15 to c8 0x00 0x43 ed/hd cgms data 2 ed/hd cgms data bits. c7 c6 c5 c4 c3 c2 c1 c0 cgms c7 to c0 0x00 1 for use with ed/hd internal test patterns only (subaddress 0x31, bit 2 = 1). table 22. register 0x44 to register 0x57 sr7 to bit number register reset sr0 register bit description 7 6 5 4 3 2 1 0 setting value 0x44 ed/hd gamma a0 ed/hd gamma curve a (point 24). x x x x x x x x a0 0x00 0x45 ed/hd gamma a1 ed/hd gamma curve a (point 32). x x x x x x x x a1 0x00 0x46 ed/hd gamma a2 ed/hd gamma curve a (point 48). x x x x x x x x a2 0x00 0x47 ed/hd gamma a3 ed/hd gamma curve a (point 64). x x x x x x x x a3 0x00 0x48 ed/hd gamma a4 ed/hd gamma curve a (point 80). x x x x x x x x a4 0x00 0x49 ed/hd gamma a5 ed/hd gamma curve a (point 96). x x x x x x x x a5 0x00 0x4a ed/hd gamma a6 ed/hd gamma curve a (point 128). x x x x x x x x a6 0x00 0x4b ed/hd gamma a7 ed/hd gamma curve a (point 160). x x x x x x x x a7 0x00 0x4c ed/hd gamma a8 ed/hd gamma curve a (point 192). x x x x x x x x a8 0x00 0x4d ed/hd gamma a9 ed/hd gamma curve a (point 224). x x x x x x x x a9 0x00 0x4e ed/hd gamma b0 ed/hd gamma curve b (poi nt 24). x x x x x x x x b0 0x00 0x4f ed/hd gamma b1 ed/hd gamma curve b (poi nt 32). x x x x x x x x b1 0x00 0x50 ed/hd gamma b2 ed/hd gamma curve b (point 48). x x x x x x x x b2 0x00 0x51 ed/hd gamma b3 ed/hd gamma curve b (point 64). x x x x x x x x b3 0x00 0x52 ed/hd gamma b4 ed/hd gamma curve b (point 80). x x x x x x x x b4 0x00 0x53 ed/hd gamma b5 ed/hd gamma curve b (point 96). x x x x x x x x b5 0x00 0x54 ed/hd gamma b6 ed/hd gamma curve b (point 128). x x x x x x x x b6 0x00 0x55 ed/hd gamma b7 ed/hd gamma curve b (point 160). x x x x x x x x b7 0x00 0x56 ed/hd gamma b8 ed/hd gamma curve b (point 192). x x x x x x x x b8 0x00 0x57 ed/hd gamma b9 ed/hd gamma curve b (point 224). x x x x x x x x b9 0x00
ADV7342/adv7343 rev. 0 | page 35 of 88 table 23. register 0x58 to register 0x5d sr7 to bit number register reset sr0 register bit description 7 6 5 4 3 2 1 0 setting value 0 0 0 0 gain a = 0 0x00 0 0 0 1 gain a = +1 0 1 1 1 gain a = +7 1 0 0 0 gain a = ?8 ed/hd adaptive filter gain 1, value a. 1 1 1 1 gain a = ?1 0 0 0 0 gain b = 0 0 0 0 1 gain b = +1 0 1 1 1 gain b = +7 1 0 0 0 gain b = ?8 0x58 ed/hd adaptive filter gain 1 ed/hd adaptive filter gain 1, value b. 1 1 1 1 gain b = ?1 0 0 0 0 gain a = 0 0x00 0 0 0 1 gain a = +1 0 1 1 1 gain a = +7 1 0 0 0 gain a = ?8 ed/hd adaptive filter gain 2, value a. 1 1 1 1 gain a = ?1 0 0 0 0 gain b = 0 0 0 0 1 gain b = +1 0 1 1 1 gain b = +7 1 0 0 0 gain b = ?8 0x59 ed/hd adaptive filter gain 2 ed/hd adaptive filter gain 2, value b. 1 1 1 1 gain b = ?1 0 0 0 0 gain a = 0 0x00 0 0 0 1 gain a = +1 0 1 1 1 gain a = +7 1 0 0 0 gain a = ?8 ed/hd adaptive filter gain 3, value a. 1 1 1 1 gain a = ?1 0 0 0 0 gain b = 0 0 0 0 1 gain b = +1 0 1 1 1 gain b = +7 1 0 0 0 gain b = ?8 0x5a ed/hd adaptive filter gain 3 ed/hd adaptive filter gain 3, value b. 1 1 1 1 gain b = ?1 0x5b ed/hd adaptive filter threshold a ed/hd adaptive filter threshold a. x x x x x x x x threshold a 0x00 0x5c ed/hd adaptive filter threshold b ed/hd adaptive filter threshold b. x x x x x x x x threshold b 0x00 0x5d ed/hd adaptive filter threshold c ed/hd adaptive filter threshold c. x x x x x x x x threshold c 0x00
ADV7342/adv7343 rev. 0 | page 36 of 88 table 24. register 0x5e to register 0x6e sr7 to bit number register reset sr0 register bit description 7 6 5 4 3 2 1 0 setting value 0 disabled 0x00 ed/hd cgms type b enable. 1 enabled 0 disabled ed/hd cgms type b crc enable. 1 enabled 0x5e ed/hd cgms type b register 0 ed/hd cgms type b header bits. h5 h4 h3 h2 h1 h0 h5 to h0 0x5f ed/hd cgms type b register 1 ed/hd cgms type b data bits. p7 p6 p5 p4 p3 p2 p1 p0 p7 to p0 0x00 0x60 ed/hd cgms type b register 2 ed/hd cgms type b data bits. p15 p14 p13 p12 p11 p10 p9 p8 p15 to p8 0x00 0x61 ed/hd cgms type b register 3 ed/hd cgms type b data bits. p23 p22 p21 p20 p19 p18 p17 p16 p23 to p16 0x00 0x62 ed/hd cgms type b register 4 ed/hd cgms type b data bits. p31 p30 p29 p28 p27 p26 p25 p24 p31 to p24 0x00 0x63 ed/hd cgms type b register 5 ed/hd cgms type b data bits. p39 p38 p37 p36 p35 p34 p33 p32 p39 to p32 0x00 0x64 ed/hd cgms type b register 6 ed/hd cgms type b data bits. p47 p46 p45 p44 p43 p42 p41 p40 p47 to p40 0x00 0x65 ed/hd cgms type b register 7 ed/hd cgms type b data bits. p55 p54 p53 p52 p51 p50 p49 p48 p55 to p48 0x00 0x66 ed/hd cgms type b register 8 ed/hd cgms type b data bits. p63 p62 p61 p60 p59 p58 p57 p56 p63 to p56 0x00 0x67 ed/hd cgms type b register 9 ed/hd cgms type b data bits. p71 p70 p69 p68 p67 p66 p65 p64 p71 to p64 0x00 0x68 ed/hd cgms type b register 10 ed/hd cgms type b data bits. p79 p78 p77 p76 p75 p74 p73 p72 p79 to p72 0x00 0x69 ed/hd cgms type b register 11 ed/hd cgms type b data bits. p87 p86 p85 p84 p83 p82 p81 p80 p87 to p80 0x00 0x6a ed/hd cgms type b register 12 ed/hd cgms type b data bits. p95 p94 p93 p92 p91 p90 p89 p88 p95 to p88 0x00 0x6b ed/hd cgms type b register 13 ed/hd cgms type b data bits. p103 p102 p101 p100 p99 p98 p97 p96 p103 to p96 0x00 0x6c ed/hd cgms type b register 14 ed/hd cgms type b data bits. p111 p110 p109 p108 p107 p106 p105 p104 p111 to p104 0x00 0x6d ed/hd cgms type b register 15 ed/hd cgms type b data bits. p119 p118 p117 p116 p115 p114 p113 p112 p119 to p112 0x00 0x6e ed/hd cgms type b register 16 ed/hd cgms type b data bits. p127 p126 p125 p124 p123 p122 p121 p120 p127 to p120 0x00
ADV7342/adv7343 rev. 0 | page 37 of 88 table 25. register 0x80 to register 0x83 sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0 0 ntsc. 0x10 0 1 pal b/d/g/h/i. 1 0 pal m. sd standard. 1 1 pal n. 0 0 0 lpf ntsc. 0 0 1 lpf pal. 0 1 0 notch ntsc. 0 1 1 notch pal. 1 0 0 ssaf luma. 1 0 1 luma cif. 1 1 0 luma qcif. sd luma filter. 1 1 1 reserved. 0 0 0 1.3 mhz. 0 0 1 0.65 mhz. 0 1 0 1.0 mhz. 0 1 1 2.0 mhz. 1 0 0 reserved. 1 0 1 chroma cif. 1 1 0 chroma qcif. 0x80 sd mode register 1 sd chroma filter. 1 1 1 3.0 mhz. 0 disabled. sd prpb ssaf. 1 enabled. 0x0b 0 sd dac output 1. 1 refer to table 32 in the output configuration section. 0 sd dac output 2. 1 refer to table 32 in the output configuration section. 0 disabled. sd pedestal. 1 enabled. 0 disabled. sd square pixel mode. 1 enabled. 0 disabled. sd vcr ff/rw sync. 1 enabled. 0 disabled. sd pixel data valid. 1 enabled. 0 disabled. 0x82 sd mode register 2 sd active video edge control. 1 enabled. 0 no pedestal on yprpb. sd pedestal on yprpb output. 1 7.5 ire pedestal on yprpb. 0x04 0 y = 700 mv/300 mv. sd output levels y. 1 y = 714 mv/286 mv. 0 0 700 mv p-p (pal), 1000 mv p-p (ntsc). 0 1 700 mv p-p. 1 0 1000 mv p-p. sd output levels prpb. 1 1 648 mv p-p. 0 disabled. sd vbi open. 1 enabled. 0 0 closed captioning disabled. 0 1 closed captioning on odd field only. 1 0 closed captioning on even field only. sd closed captioning field control. 1 1 closed captioning on both fields. 0x83 sd mode register 3 reserved. 0 reserved.
ADV7342/adv7343 rev. 0 | page 38 of 88 table 26. register 0x84 to register 0x89 sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0 disabled. 0x00 sd vsync -3h. 1 vsync = 2.5 lines (pal), vsync = 3 lines (ntsc). 0 0 disabled. 0 1 subcarrier phase reset mode enabled. 1 0 timing reset mode enabled. sd sfl/scr/tr mode select. 1 1 sfl mode enabled. 0 720 pixels. sd active video length. 1 710 (ntsc), 702 (pal). 0 chroma enabled. sd chroma. 1 chroma disabled. 0 enabled. sd burst. 1 disabled. 0 disabled. sd color bars. 1 enabled. 0 dac 2 = luma, dac 3 = chroma. 0x84 sd mode register 4 sd luma/chroma swap. 1 dac 2 = chroma, dac 3 = luma. 0 0 5.17 s. 0x02 0 1 5.31 s. 1 0 5.59 s (must be set for macrovision compliance). ntsc color subcarrier adjust (delay from the falling edge of output hsync pulse to start of color burst). 1 1 reserved. reserved. 0 0 disabled. sd eia/cea-861b synchronization compliance. 1 enabled. reserved. 0 0 0 update field/line counter. sd horizontal/vertical counter mode. 1 1 field/line counter free running. 0 normal. 0x86 sd mode register 5 sd rgb color swap. 1 color reversal enabled. 0 disabled. 0x00 sd prpb scale. 1 enabled. 0 disabled. sd y scale. 1 enabled. 0 disabled. sd hue adjust. 1 enabled. 0 disabled. sd brightness. 1 enabled. 0 disabled. sd luma ssaf gain. 1 enabled. 0 disabled. sd input standard auto detect. 1 enabled. reserved. 0 0 must be written to this bit. 0 sd ycrcb input. 0x87 sd mode register 6 sd rgb input enable. 1 sd rgb input.
ADV7342/adv7343 rev. 0 | page 39 of 88 sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value reserved. 0 0x00 0 disabled. sd noninterlaced mode. 1 enabled. 0 disabled. sd double buffering. 1 enabled. 0 0 8-bit input. 0 1 16-bit input. 1 0 reserved. sd input format. 1 1 reserved. 0 disabled. sd digital noise reduction. 1 enabled. 0 disabled. sd gamma correction enable. 1 enabled. 0 gamma correction curve a. 0x88 sd mode register 7 sd gamma correction curve select. 1 gamma correction curve b. 0 0 disabled. 0x00 0 1 ?11 ire. 1 0 ?6 ire. sd undershoot limiter. 1 1 ?1.5 ire. reserved. 0 0 must be written to this bit. 0 disabled. sd black burst output on dac luma. 1 enabled. 0 0 disabled. 0 1 4 clock cycles. 1 0 8 clock cycles. sd chroma delay. 1 1 reserved. 0x89 sd mode register 8 reserved. 0 0 0 must be written to these bits. 1 when set to 0, the horizontal/vertical counters automatically wr ap around at the end of the line/field/frame of the selected s tandard. when set to 1, the horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
ADV7342/adv7343 rev. 0 | page 40 of 88 table 27. register 0x8a to register 0x98 sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0 slave mode. 0x08 sd slave/master mode. 1 master mode. 0 0 mode 0. 0 1 mode 1. 1 0 mode 2. sd timing mode. 1 1 mode 3. reserved. 1 0 0 no delay. 0 1 2 clock cycles. 1 0 4 clock cycles. sd luma delay. 1 1 6 clock cycles. 0 ?40 ire. sd minimum luma value. 1 ?7.5 ire. 0x8a sd timing register 0 sd timing reset. x a low-high-low transition resets the internal sd timing counters. 0 0 t a = 1 clock cycle. 0x00 0 1 t a = 4 clock cycles. 1 0 t a = 16 clock cycles. sd hsync width. 1 1 t a = 128 clock cycles. 0 0 t b = 0 clock cycles. 0 1 t b = 4 clock cycles. 1 0 t b = 8 clock cycles. sd hsync to vsync delay. 1 1 t b = 18 clock cycles. x 0 t c = t b . sd hsync to vsync rising edge delay (mode 1 only). x 1 t c = t b + 32 s. 0 0 1 clock cycle. 0 1 4 clock cycles. 1 0 16 clock cycles. sd vsync width (mode 2 only). 1 1 128 clock cycles. 0 0 0 clock cycles. 0 1 1 clock cycle. 1 0 2 clock cycles. 0x8b sd timing register 1 (note: applicable in master modes only, that is, subaddress 0x8a, bit 0 = 1) sd hsync to pixel data adjust. 1 1 3 clock cycles. 0x8c sd f sc register 0 1 subcarrier frequency bits[7:0]. x x x x x x x x subcarrier frequency bits[7:0]. 0x1f 0x8d sd f sc register 1 1 subcarrier frequency bits[15:8]. x x x x x x x x subcarrier frequency bits[15:8]. 0x7c 0x8e sd f sc register 2 1 subcarrier frequency bits[23:16]. x x x x x x x x subcarrier frequency bits[23:16]. 0xf0 0x8f sd f sc register 3 1 subcarrier frequency bits[31:24]. x x x x x x x x subcarrier frequency bits[31:24]. 0x21 0x90 sd f sc phase subcarrier phase bits[9:2]. x x x x x x x x subcarrier phase bits[9:2]. 0x00 0x91 sd closed captioning extended data on even fields. x x x x x x x x extended data bits[7:0]. 0x00 0x92 sd closed captioning extended data on even fields. x x x x x x x x extended data bits[15:8]. 0x00 0x93 sd closed captioning data on odd fields. x x x x x x x x data bits[7:0]. 0x00 0x94 sd closed captioning data on odd fields. x x x x x x x x data bits[15:8]. 0x00 0x95 sd pedestal register 0 pedestal on odd fields. 17 16 15 14 13 12 11 10 0x00 0x96 sd pedestal register 1 pedestal on odd fields. 25 24 23 22 21 20 19 18 0x00 0x97 sd pedestal register 2 pedestal on even fields. 17 16 15 14 13 12 11 10 0x00 0x98 sd pedestal register 3 pedestal on even fields. 25 24 23 22 21 20 19 18 setting any of these bits to 1 disables pedestal on the line number indicated by the bit settings. 0x00 1 sd subcarrier frequency registers defaul t to ntsc subcarrier frequency values.
ADV7342/adv7343 rev. 0 | page 41 of 88 table 28. register 0x99 to register 0xa5 sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value sd cgms data. x x x x cgms data bits[c19:c16] 0x00 0 disabled sd cgms crc. 1 enabled 0 disabled sd cgms on odd fields. 1 enabled 0 disabled sd cgms on even fields. 1 enabled 0 disabled 0x99 sd cgms/wss 0 sd wss. 1 enabled 0x00 sd cgms/wss data. x x x x x x cgms data bits[c13:c8] or wss data bits[w13:w8] 0x9a sd cgms/wss 1 sd cgms data. x x cgms data bits[c15:c14] 0x9b sd cgms/wss 2 sd cgms/wss data. x x x x x x x x cgms data bits[c7:c0] or wss data bits[w7:w0] 0x00 lsbs for sd y scale value. x x sd y scale bits[1:0] 0x00 lsbs for sd cb scale value. x x sd cb scale bits[1:0] lsbs for sd cr scale value. x x sd cr scale bits[1:0]. 0x9c sd scale lsb register lsbs for sd f sc phase. x x subcarrier phase bits[1:0] 0x9d sd y scale register sd y scale value. x x x x x x x x sd y scale bits[9:2] 0x00 0x9e sd cb scale register sd cb scale value. x x x x x x x x sd cb scale bits[9:2] 0x00 0x9f sd cr scale register sd cr scale value. x x x x x x x x sd cr scale bits[9:2] 0x00 0xa0 sd hue register sd hue adjust value. x x x x x x x x sd hue adjust bits[7:0] 0x00 sd brightness value. x x x x x x x sd brightness bits[6:0] 0x00 0 disabled 0xa1 sd brightness/wss sd blank wss data. 1 enabled 0 0 0 0 ?4 db 0x00 0 1 1 0 0 db sd luma ssaf gain/attenuation. note: only applicable if register 0x87, bit 4 = 1. 1 1 0 0 +4 db 0xa2 sd luma ssaf reserved. 0 0 0 0 0 0 0 0 no gain 0x00 0 0 0 1 +1/16 [?1/8] 0 0 1 0 +2/16 [?2/8] 0 0 1 1 +3/16 [?3/8] 0 1 0 0 +4/16 [?4/8] 0 1 0 1 +5/16 [?5/8] 0 1 1 0 +6/16 [?6/8] 0 1 1 1 +7/16 [?7/8] coring gain border. note: in dnr mode, the values in brackets apply. 1 0 0 0 +8/16 [?1] 0 0 0 0 no gain 0 0 0 1 +1/16 [?1/8] 0 0 1 0 +2/16 [?2/8] 0 0 1 1 +3/16 [?3/8] 0 1 0 0 +4/16 [?4/8] 0 1 0 1 +5/16 [?5/8] 0 1 1 0 +6/16 [?6/8] 0 1 1 1 +7/16 [?7/8] 0xa3 sd dnr 0 coring gain data. note: in dnr mode, the values in brackets apply. 1 0 0 0 +8/16 [?1]
ADV7342/adv7343 rev. 0 | page 42 of 88 sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0 0 0 0 0 0 0 0x00 0 0 0 0 0 1 1 1 1 1 1 1 0 62 dnr threshold. 1 1 1 1 1 1 63 0 2 pixels border area. 1 4 pixels 0 8 pixels 0xa4 sd dnr 1 block size control. 1 16 pixels 0 0 1 filter a 0x00 0 1 0 filter b 0 1 1 filter c dnr input select. 1 0 0 filter d 0 dnr mode dnr mode. 1 dnr sharpness mode 0 0 0 0 0 pixel offset 0 0 0 1 1 pixel offset 1 1 1 0 14 pixel offset 0xa5 sd dnr 2 dnr block offset. 1 1 1 1 15 pixel offset table 29. register 0xa6 to register 0xbb sr7 to bit number register reset sr0 register bit description 7 6 5 4 3 2 1 0 setting value 0xa6 sd gamma a 0 sd gamma curve a (point 24). x x x x x x x x a0 0x00 0xa7 sd gamma a 1 sd gamma curve a (point 32). x x x x x x x x a1 0x00 0xa8 sd gamma a 2 sd gamma curve a (point 48). x x x x x x x x a2 0x00 0xa9 sd gamma a 3 sd gamma curve a (point 64). x x x x x x x x a3 0x00 0xaa sd gamma a 4 sd gamma curve a (point 80). x x x x x x x x a4 0x00 0xab sd gamma a 5 sd gamma curve a (point 96). x x x x x x x x a5 0x00 0xac sd gamma a 6 sd gamma curve a (point 128). x x x x x x x x a6 0x00 0xad sd gamma a 7 sd gamma curve a (point 160). x x x x x x x x a7 0x00 0xae sd gamma a 8 sd gamma curve a (point 192). x x x x x x x x a8 0x00 0xaf sd gamma a 9 sd gamma curve a (point 224). x x x x x x x x a9 0x00 0xb0 sd gamma b 0 sd gamma curve b (point 24). x x x x x x x x b0 0x00 0xb1 sd gamma b 1 sd gamma curve b (point 32). x x x x x x x x b1 0x00 0xb2 sd gamma b 2 sd gamma curve b (point 48). x x x x x x x x b2 0x00 0xb3 sd gamma b 3 sd gamma curve b (point 64). x x x x x x x x b3 0x00 0xb4 sd gamma b 4 sd gamma curve b (point 80). x x x x x x x x b4 0x00 0xb5 sd gamma b 5 sd gamma curve b (point 96). x x x x x x x x b5 0x00 0xb6 sd gamma b 6 sd gamma curve b (point 128). x x x x x x x x b6 0x00 0xb7 sd gamma b 7 sd gamma curve b (point 160). x x x x x x x x b7 0x00 0xb8 sd gamma b 8 sd gamma curve b (point 192). x x x x x x x x b8 0x00 0xb9 sd gamma b 9 sd gamma curve b (point 224). x x x x x x x x b9 0x00 0xba sd brightness detect sd brightness value. x x x x x x x x read only. 0xxx field count. x x x read only. 0x0x reserved. 0 0 0 reserved. 0xbb field count register revision code. 0 0 read only.
ADV7342/adv7343 rev. 0 | page 43 of 88 table 30. register 0xe0 to register 0xf1 sr7 to bit number reset sr0 register 1 bit description 7 6 5 4 3 2 1 0 register setting value 0xe0 macrovision mv control bits. x x x x x x x x 0x00 0xe1 macrovision mv control bits. x x x x x x x x 0x00 0xe2 macrovision mv control bits. x x x x x x x x 0x00 0xe3 macrovision mv control bits. x x x x x x x x 0x00 0xe4 macrovision mv control bits. x x x x x x x x 0x00 0xe5 macrovision mv control bits. x x x x x x x x 0x00 0xe6 macrovision mv control bits. x x x x x x x x 0x00 0xe7 macrovision mv control bits. x x x x x x x x 0x00 0xe8 macrovision mv control bits. x x x x x x x x 0x00 0xe9 macrovision mv control bits. x x x x x x x x 0x00 0xea macrovision mv control bits. x x x x x x x x 0x00 0xeb macrovision mv control bits. x x x x x x x x 0x00 0xec macrovision mv control bits. x x x x x x x x 0x00 0xed macrovision mv control bits. x x x x x x x x 0x00 0xee macrovision mv control bits. x x x x x x x x 0x00 0xef macrovision mv control bits. x x x x x x x x 0x00 0xf0 macrovision mv control bits. x x x x x x x x 0x00 0xf1 macrovision mv control bit. 0 0 0 0 0 0 0 x bits[7:1] must be 0. 0x00 1 macrovision registers are av ailable on the ADV7342 only.
ADV7342/adv7343 rev. 0 | page 44 of 88 input configuration the ADV7342/adv7343 support a number of different input modes. the desired input mode is selected using subaddress 0x01, bits[6:4]. the ADV7342/adv7343 default to standard definition only (sd only) upon power-up. table 31 provides an overview of all possible input configurations. each input mode is described in detail in the following sections. standard definition only subaddress 0x01, bits[6:4] = 000 standard definition (sd) ycrcb data can be input in 4:2:2 format. standard definition (sd) rgb data can be input in 4:4:4 format. a 27 mhz clock signal must be provided on the clkin_a pin. input synchronization signals are provided on the s_hsync and s_vsync pins. 8-bit 4:2:2 ycrcb mode subaddress 0x87, bit 7 = 0; subaddress 0x88, bit 3 = 0 in 8-bit 4:2:2 ycrcb input mode, the interleaved pixel data is input on pin s7 to pin s0 (or pin y7 to pin y0, depending on subaddress 0x01, bit 7), with s0/y0 being the lsb. the itu-r bt.601/656 input standard is supported. 16-bit 4:2:2 ycrcb mode subaddress 0x87, bit 7 = 0; subaddress 0x88, bit 3 = 1 in 16-bit 4:2:2 ycrcb input mode, the y pixel data is input on pin s7 to pin s0 (or pin y7 to pin y0, depending on subaddress 0x01, bit 7), with s0/y0 being the lsb. the crcb pixel data is input on pin y7 to pin y0 (or pin c7 to pin c0, depending on subaddress 0x01, bit 7), with y0/c0 being the lsb. 24-bit 4:4:4 rgb mode subaddress 0x87, bit 7 = 1 in 24-bit 4:4:4 rgb input mode, the red pixel data is input on pin s7 to pin s0, the green pixel data is input on pin y7 to pin y0, and the blue pixel data is input on pin c7 to pin c0. s0, y0, and c0 are the respective bus lsbs. table 31. input configuration s y c input mode 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 000 sd only y/c/s bus swap (0x01[7]) = 0 8-bit ycrcb 2 ycrcb 16-bit ycrcb 2, 3 y crcb y/c/s bus swap (0x01[7]) = 1 8-bit ycrcb 2 ycrcb 16-bit ycrcb 2, 3 y crcb sd rgb input enable (0x87[7]) = 1 24-bit rgb 3 r g b 001 ed/hd-sdr only 4, 5 ed/hd rgb input enable (0x35[1]) = 0 16-bit ycrcb y crcb 24-bit ycrcb cr y cb ed/hd rgb input enable (0x35[1]) = 1 24-bit rgb 3 r g b 010 ed/hd-ddr only (8-bit) 5 ycrcb 011 sd and ed/hd-sdr (24-bit) 5 ycrcb (sd) y (ed/hd) crcb (ed/hd) 100 sd and ed/hd-ddr (16-bit) 5 ycrcb (sd) ycrcb (ed/hd) 111 ed only (54 mhz) (8-bit) 5 ycrcb 1 the input mode is determined by subaddress 0x01, bits[6:4]. 2 in sd only (ycrcb) mode, the format of the input data is determined by subaddress 0x88, bits[4:3]. see table 26 for more infor mation. 3 external synchronization signals must be used in this input mode. embedded eav/sav timing codes are not supported. 4 in ed/hd-sdr only (ycrcb) mode, the format of the input data is determined by subaddress 0x33, bit 6. see table 19 for more in formation. 5 ed = enhanced definition = 525p and 625p.
ADV7342/adv7343 rev. 0 | page 45 of 88 mpeg2 decoder clkin_a s[7:0] or y[7:0]* 27mhz ycrcb ADV7342/ adv7343 * selected by subaddress 0x01, bit 7. s_vsync, s_hsync 2 10 06399-051 figure 51. sd only example application enhanced definition/hig h definition only subaddress 0x01, bits[6:4] = 001 or 010 enhanced definition (ed) or high definition (hd) ycrcb data can be input in either 4:2:2 or 4:4:4 formats if desired, dual data rate (ddr) pixel data inputs can be employed (4:2:2 format only) enhanced definition (ed) or high definition (hd) rgb data can be input in 4:4:4 format (single data rate only) the clock signal must be provided on the cina pin input synchronization signals are provided on the phsync , pvsync , and pban pins 16-bit 4:2:2 ycrcb mode (sdr) subaddress 0x35, bit 1 = 0; subaddress 0x33, bit 6 = 1 in 16-bit 4:2:2 ycrcb input mode, the y pixel data is input on pin y7 to pin y0, with y0 being the sb the crcb pixel data is input on pin c7 to pin c0, with c0 being the sb 8-bit 4:2:2 ycrcb mode (ddr) subaddress 0x35, bit 1 = 0; subaddress 0x33, bit 6 = 1 in 8-bit ddr 4:2:2 ycrcb input mode, the y pixel data is input on pin y7 to pin y0 upon either the rising or falling edge of cina y0 is the sb the crcb pixel data is also input on pin y7 to pin y0 upon the opposite edge of cina y0 is the sb hether the y data is clocked in upon the rising or falling edge of cina is determined by subaddress 0x01, bits[2:1] (see figure 52 and figure 53) 3ff 00 00 x yy0 y1 cr0 clkin_a notes 1. subaddress 0x01 [2:1] should be set to 00 in this case. y[7:0] cb0 06399-052 figure 52. ed/hd-ddr input sequence (eav/sav)option a 3ff 00 00 xy cb0 cr0 y1 clkin_ a y[7:0] y0 notes 1. subaddress 0x01 [2:1] should be set to11 in this case. 06399-053 figure 53. ed/hd-ddr input sequence (eav/sav)option b 24-bit 4:4:4 ycrcb mode subaddress 0x35, bit 1 = 0; subaddress 0x33, bit 6 = 0 in 24-bit 4:4:4 ycrcb input mode, the y pixel data is input on pin y7 to pin y0, with y0 being the sb the cr pixel data is input on pin s7 to pin s0, with s0 being the sb the cb pixel data is input on pin c7 to pin c0, with c0 being the sb 24-bit 4:4:4 rgb mode subaddress 0x35, bit 1 = 1 in 24-bit 4:4:4 rgb input mode, the red pixel data is input on pin s7 to pin s0, the green pixel data is input on pin y7 to pin y0, and the blue pixel data is input on pin c7 to pin c0 s0, y0, and c0 are the respective bus sbs mpeg2 decoder clkin_ a c[7:0] s[7:0] y[7:0] interlaced to progressive ycrcb p_vsync, p_hsync, p_blank 10 cb 10 cr 10 y 3 06399-054 ADV7342/ adv7343 figure 54. ed/hd only example application simultaneous standard definition and enhanced definition /high definition subaddress 0x01, bits[6:4] = 011 or 100 the ADV7342/adv7343 are able to simultaneously process sd 4:2:2 ycrcb data and ed/hd 4:2:2 ycrcb data the 27 mhz sd clock signal must be provided on the cina pin the ed/hd clock signal must be provided on the cinb pin sd input synchronization signals are provided on the shsync and svsync pins ed/hd input synchronization signals are provided on the phsync , pvsync and pban pins sd 8-bit 4:2:2 ycrcb and ed /hd-sdr 16-bit 4:2:2 ycrcb the sd 8-bit 4:2:2 ycrcb pixel data is input on pin s7 to pin s0, with s0 being the sb the ed/hd 16-bit 4:2:2 y pixel data is input on pin y7 to pin y0, with y0 being the sb the ed/hd 16-bit 4:2:2 crcb pixel data is input on pin c7 to pin c0, with c0 being the sb sd 8-bit 4:2:2 ycrcb and ed /hd-ddr 8-bit 4:2:2 ycrcb the sd 8-bit 4:2:2 ycrcb pixel data is input on pin s7 to pin s0, with s0 being the sb the ed/hd-ddr 8-bit 4:2:2 y pixel data is input on pin y7 to pin y0 upon the rising or falling edge of cinb y0 is the sb the ed/hd-ddr 8-bit 4:2:2 crcb pixel data is also input on pin y7 to pin y0 upon the opposite edge of cinb y0 is the sb
ADV7342/adv7343 rev. 0 | page 46 of 88 whether the ed/hd y data is clocked in upon the rising or falling edge of clkin_b is determined by subaddress 0x01, bits[2:1] (see the input sequence shown in figure 52 and figure 53). clkin_a clkin_b s[7:0] c[7:0] y[7:0] hdtv decoder s_hsync p_vsync, p_hsync, p_blank 74.25mhz 10 crcb crcb 10 y 3 2 ycrcb 27mhz 10 sdtv decoder 1080i or 720p or 1035i 06399-055 ADV7342/ adv7343 s_vsync, figure 55. simultaneous sd and ed example application clkin_a clkin_b s[7:0] c[7:0] y[7:0] hdtv decoder s_vsync, s_hsync p_vsync, p_hsync, p_blank 74.25mhz 10 crcb 10 y 3 2 ycrcb 27mhz 10 sdtv decoder 1080i or 720p or 1035i 06399-056 ADV7342/ adv7343 figure 56. simultaneous sd and hd example application enhanced definition only (at 54 mhz) subaddress 0x01, bits[6:4] 111 enhanced definition (ed) ycrcb data can be input in an interleaved 4:2:2 format on an 8-bit bus at a rate of 54 mhz. a 54 mhz clock signal must be provided on the clkin_a pin. input synchronization signals are provided on the p_hsync , p_vsync , and p_blank pins. the interleaved pixel data is input on pin y7 to pin y0, with y0 being the lsb. 3ff 00 00 xy cb0 y0 y1 cr0 clkin_a y[7:0] 06399-057 figure 57. ed only (at 54 mhz) input sequence (eav/sav) mpeg2 deco der clkin_a y[7:0] 54mhz ADV7342/ adv7343 p_vsync, p_hsync, p_blank ycrcb 10 ycrcb 3 interlaced to progressive 06399-058 figure 58. ed only (at 54 mhz) example application
ADV7342/adv7343 rev. 0 | page 47 of 88 output configuration the ADV7342/adv7343 support a number of different output configurations. table 32 to table 35 lists all possible output configu rations. table 32. sd only output configurations rgb/yprpb output select 1 (0x02, bit 5) sd dac output 2 (0x82, bit 2) sd dac output 1 (0x82, bit 1) sd luma/chroma swap (0x84, bit 7) dac 1 dac 2 dac 3 dac 4 dac 5 dac 6 0 0 0 0 g b r cvbs luma chroma 0 0 0 1 g b r cvbs chroma luma 0 0 1 0 cvbs luma chroma g b r 0 0 1 1 cvbs chroma luma g b r 0 1 0 0 cvbs b r g luma chroma 0 1 0 1 cvbs b r g chroma luma 0 1 1 0 g luma chroma cvbs b r 0 1 1 1 g chroma luma cvbs b r 1 0 0 0 y pb pr cvbs luma chroma 1 0 0 1 y pb pr cvbs chroma luma 1 0 1 0 cvbs luma chroma y pb pr 1 0 1 1 cvbs chroma luma y pb pr 1 1 0 0 cvbs pb pr y luma chroma 1 1 0 1 cvbs pb pr y chroma luma 1 1 1 0 y luma chroma cvbs pb pr 1 1 1 1 y chroma luma cvbs pb pr 1 if sd rgb output is selected, a color reversal is possible using subaddress 0x86, bit 7. table 33. ed/hd only output configurations rgb/yprpb output select (0x02, bit 5) ed/hd color dac swap (0x35, bit 3) dac 1 dac 2 dac 3 dac 4 dac 5 dac 6 0 0 g b r n/a n/a n/a 0 1 g r b n/a n/a n/a 1 0 y pb pr n/a n/a n/a 1 1 y pr pb n/a n/a n/a table 34. simultaneous sd and ed/hd output configurations rgb/yprpb output select (0x02, bit 5) ed/hd color dac swap (0x35, bit 3) sd luma/chroma swap (0x84, bit 7) dac 1 (ed/hd) dac 2 (ed/hd) dac 3 (ed/hd) dac 4 (sd) dac 5 (sd) dac 6 (sd) 0 0 0 g b r cvbs luma chroma 0 0 1 g b r cvbs chroma luma 0 1 0 g r b cvbs luma chroma 0 1 1 g r b cvbs chroma luma 1 0 0 y pb pr cvbs luma chroma 1 0 1 y pb pr cvbs chroma luma 1 1 0 y pr pb cvbs luma chroma 1 1 1 y pr pb cvbs chroma luma table 35. ed only (at 54 mhz) output configurations rgb/yprpb output select (0x02, bit 5) ed/hd color dac swap (0x35, bit 3) dac 1 dac 2 dac 3 dac 4 dac 5 dac 6 0 0 g b r n/a n/a n/a 0 1 g r b n/a n/a n/a 1 0 y pb pr n/a n/a n/a 1 1 y pr pb n/a n/a n/a
ADV7342/adv7343 rev. 0 | page 48 of 88 features output oversampling the ADV7342/adv7343 include two on-chip phase locked loops (plls) that allow for oversampling of sd, ed, and hd video data. table 36 shows the various oversampling rates supported in the ADV7342/adv7343. sd only, ed only, and hd only modes pll 1 is used in sd only, ed only, and hd only modes. pll 2 is unused in these modes. pll 1 is disabled by default and can be enabled using subaddress 0x00, bit 1 = 0. sd and ed/hd simultaneous modes both pll 1 and pll 2 are used in simultaneous modes. the use of two plls allows for independent oversampling of sd and ed/hd video. pll 1 is used to oversample sd video data, and pll 2 is used to oversample ed/hd video data. in simultaneous modes, pll 2 is always enabled. pll 1 is disabled by default and can be enabled using subaddress 0x00, bit 1 = 0. ed/hd nonstandard timing mode subaddress 0x30, bits[7:3] = 00001 for any ed/hd input data that does not conform to the standards available in the ed/hd input mode table (subaddress 0x30, bits[7:3]), the ed/hd nonstandard timing mode can be used to interface to the ADV7342/adv7343. ed/hd nonstandard timing mode can be enabled by setting subaddress 0x30, bits[7:3] to 00001. a clock signal must be provided on the clkin_a pin. p_hsync and p_vsync must be toggled by the user to generate the appropriate horizontal and vertical synchronization pulses on the analog output from the encoder. figure 59 illustrates the various output levels that can be generated .table 37 lists the transitions required to generate these output levels. embedded eav/sav timing codes are not supported in ed/hd nonstandard timing mode. the user must ensure that appropriate pixel data is applied to the encoder where the blanking level is expected at the output. macrovision (ADV7342 only) and output oversampling are not available in ed/hd nonstandard timing mode. active video a n a log output a b c b b a = tri-level synchronization pulse level. b = blanking level/active video level. c = synchronization pulse level. blanking level 06399-141 figure 59. ed/hd nonstandard timing mode output levels table 36. output oversampling modes and rates input mode subaddress 0x01 [6:4] pll and oversampling control subaddress 0x00, bit 1 oversampling mode and rate 000 sd only 1 sd (2) 000 sd only 0 sd (16) 001/010 ed only 1 ed (1) 001/010 ed only 0 ed (8) 001/010 hd only 1 hd (1) 001/010 hd only 0 hd (4) 011/100 sd and ed 1 sd (2) and ed (8) 011/100 sd and ed 0 sd (16) and ed (8) 011/100 sd and hd 1 sd (2) and hd (4) 011/100 sd and hd 0 sd (16) and hd (4) 111 ed only (at 54 mhz) 1 ed only (at 54 mhz) (1) 111 ed only (at 54 mhz) 0 ed only (at 54 mhz) (8) table 37. ed/hd nonstandard timing mode synchronization signal generation output level transition 1 p_hsync p_vsync b c 1 0 1 0 or 0 2 c a 0 0 1 a b 0 1 1 c b 0 1 0 1 a = tri-level synchronization pulse level; b = blanking level/active video level; c = synchronization pulse level. 2 if p_vsync = 1, it should transition to 0. if p_vsync = 0, it should remain at 0. if tri-level sy nchronization pulse genera tion is not required, p_vsync should always be 0.
ADV7342/adv7343 rev. 0 | page 49 of 88 ed/hd timing reset subaddress 0x34, bit 0 an ed/hd timing reset is achieved by toggling the ed/hd timing reset control bit (subaddress 0x34, bit 0) from 0 to 1. in this state, the horizontal and vertical counters remain reset. when this bit is set back to 0, the internal counters resume counting. this timing reset applies to the ed/hd timing counters only. sd subcarrier frequency lock, subcarrier phase reset, and timing reset subaddress 0x84, bits[2:1] together with the sfl/miso pin and sd mode register 4 (subaddress 0x84, bits[2:1]), the ADV7342/adv7343 can be used in timing reset mode, subcarrier phase reset mode, or sfl mode. timing reset (tr) mode in this mode (subaddress 0x84, bits[2:1] = 10), a timing reset is achieved in a low-to-high transition on the sfl/miso pin (pin 48). in this state, the horizontal and vertical counters remain reset. upon releasing this pin (set to low), the internal counters resume counting, starting with field 1, and the subcarrier phase is reset. the minimum time the pin must be held high is one clock cycle; otherwise, this reset signal might not be recognized. this timing reset applies to the sd timing counters only. subcarrier phase reset (scr) mode in this mode (subaddress 0x84, bits[2:1] = 01), a low-to-high transition on the sfl/miso pin (pin 48) resets the subcarrier phase to 0 on the field following the subcarrier phase reset. this reset signal must be held high for a minimum of one clock cycle. because the field counter is not reset, it is recommended that the reset signal be applied in field 7 (pal) or field 3 (ntsc). the reset of the phase then occurs on the next field, that is, field 1, lined up correctly with the internal counters. the field count register at subaddress 0xbb can be used to identify the number of the active field. subcarrier frequency lock (sfl) mode in this mode (subaddress 0x84, bits[2:1] = 11), the ADV7342 /adv7343 can be used to lock to an external video source. the sfl mode allows the ADV7342/adv7343 to automatically alter the subcarrier frequency to compensate for line length variations. when the part is connected to a device such as an adv7403 video decoder (see figure 62) that outputs a digital data stream in the sfl format, the part automatically changes to the compensated subcarrier frequency on a line-by-line basis. this digital data stream is 67 bits wide, and the subcarrier is contained in bit 0 to bit 21. each bit is two clock cycles long. displ a y no timing reset applied timing reset applied st a rt of field 4 or 8 f sc phase = field 4 or 8 f sc phase = field 1 timing reset pulse 307 310 307 12345 67 21 313 320 display start of field 1 06399-061 figure 60. sd timing reset timing diagram (subaddress 0x84, bits [2:1] = 10) no f sc reset applied f sc phase = field 4 or 8 307 310 313 320 displ a y st a rt of field 4 or 8 f sc reset applied f sc reset pulse f sc phase = field 1 307 310 313 320 display start of field 4 or 8 06399-062 figure 61. sd subcarrier phase reset timing diagram (subaddress 0x84, bits [2:1] = 01)
ADV7342/adv7343 rev. 0 | page 50 of 88 lcc1 sfl p[19:12] adv7403 video decoder clkin_a sfl/miso y[7:0]/s[7:0] 5 rtc low 128 time slot 01 13 0 14 21 19 f sc pll increment 2 valid sample invalid sample 6768 0 reset bit 4 reserved ADV7342/adv7343 8/line locked clock 5bits reserved 1 for example, vcr or cable. 2 f sc pll increment is 22 bits long. value loaded into ADV7342/adv7343 f sc dds register is f sc pll increments bits 21:0 plus bits 0:9 of subcarrier frequency registers. 3 sequence bit pal: 0 = line normal, 1 = line inverted ntsc: 0 = no change 4 reset ADV7342/adv7343 dds. 5 selected by subaddress 0x01, bit 7. composite video 1 h/l transition count start 14 bits subcarrier phase sequence bit 3 dac 1 dac 2 dac 3 dac 4 dac 5 dac 6 4bits reserved 06399-063 figure 62. sd subcarrier frequency lock timing and connections diagram (subaddress 0x84, bits [2:1] = 11) sd vcr ff/rw sync subaddress 0x82, bit 5 in dvd record applications where the encoder is used with a decoder, the vcr ff/rw sync control bit can be used for non- standard input video, that is, in fast forward or rewind modes. in fast forward mode, the sync information at the start of a new field in the incoming video usually occurs before the correct number of lines/fields is reached. in rewind mode, this sync signal usually occurs after the total number of lines/fields is reached. conventionally, this means that the output video has corrupted field signals because one signal is generated by the incoming video and another is generated when the internal line/field counters reach the end of a field. when the vcr ff/rw sync control is enabled (subaddress 0x82, bit 5), the line/field counters are updated according to the incoming vsync signal and when the analog output matches the incoming vsync signal. this control is available in all slave-timing modes except slave mode 0. vertical blanking interval subaddress 0x31, bit 4 subaddress 0x83, bit 4 the ADV7342/adv7343 are able to accept input data that contains vbi data (such as cgms, wss, and vits) in sd, ed, and hd modes. if vbi is disabled (subaddress 0x31, bit 4 for ed/hd; subaddress 0x83, bit 4 for sd), vbi data is not present at the output and the entire vbi is blanked. these control bits are valid in all master and slave timing modes. for the smpte 293m (525p) standard, vbi data can be inserted on line 13 to line 42 of each frame, or on line 6 to line 43 for the itu-r bt.1358 (625p) standard. vbi data can be present on line 10 to line 20 for ntsc and on line 7 to line 22 for pal. in sd timing mode 0 (slave option), if vbi is enabled, the blanking bit in the eav/sav code is overwritten. it is possible to use vbi in this timing mode as well. if cgms is enabled and vbi is disabled, the cgms data is nevertheless available at the output. sd subcarrier frequency registers subaddress 0x8c to subaddress 0x8f four 8-bit registers are used to set up the subcarrier frequency. the value of these registers is calculated using: 32 2 mhz 27 = line video one in cycles clk of number line video one in periods subcarrier of number register frequency subcarrier where the sum is rounded to the nearest integer. for example, in ntsc mode: 569408543 2 1716 5 . 227 32 = ? ? ? ? ? ? = value register subcarrier where: subcarrier register value = 569408543d = 021f07c1f sd f sc register 0: 0x1f sd f sc register 1: 0x7c sd f sc register 2: 0xf0 sd f sc register 3: 0x21
ADV7342/adv7343 rev. 0 | page 51 of 88 programming the f sc the subcarrier frequency register value is divided into four f sc registers as shown in the previous example. the four subcarrier frequency registers must be updated sequentially, starting with subcarrier frequency register 0 and ending with subcarrier frequency register 3. the subcarrier frequency updates only after the last subcarrier frequency register byte has been received by the ADV7342/adv7343. typical f sc values table 38 outlines the values that should be written to the subcarrier frequency registers for ntsc and pal b/d/g/h/i. table 38. typical f sc values subaddress description ntsc pal b/d/g/h/i 0x8c f sc 0 0x1f 0xcb 0x8d f sc 1 0x7c 0x8a 0x8e f sc 2 0xf0 0x09 0x8f f sc 3 0x21 0x2a sd noninterlaced mode subaddress 0x88, bit 1 the ADV7342/adv7343 support a sd noninterlaced mode. using this mode, progressive inputs at twice the frame rate of ntsc and pal (240p/59.94 hz and 288p/50 hz, respectively) can be input into the ADV7342/adv7343. the sd noninterlaced mode can be enabled using subaddress 0x88, bit 1. a 27 mhz clock signal must be provided on the clkin_a pin. embedded eav/sav timing codes or external horizontal and vertical synchronization signals provided on the s_hsync and s_vsync pins can be used to synchronize the input pixel data. all input configurations, output configurations and features available in ntsc and pal modes are available in sd non- interlaced mode. for 240p/59.94 hz input, the ADV7342/adv7343 should be configured for ntsc operation and subaddress 0x88, bit 1 should be set to 1. for 288p/50 hz input, the ADV7342/adv7343 should be configured for pal operation and subaddress 0x88, bit 1 should be set to 1. sd square pixel mode subaddress 0x82, bit 4 the ADV7342/adv7343 can be used to operate in square pixel mode (subaddress 0x82, bit 4). for ntsc operation, an input clock of 24.5454 mhz is required. alternatively, for pal operation, an input clock of 29.5 mhz is required. the internal timing logic adjusts accordingly for square pixel mode operation. in square pixel mode, the timing diagrams shown in figure 63 and figure 64 apply. y c r y f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 f f 0 0 f f a b a b a b 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r c b y c b y c r eav code sav code ancillary data (hanc) 4 clock 4 clock 272 clock 1280 clock 4 clock 4 clock 344 clock 1536 clock end of active video line start of active video line analog video input pixels ntsc/pal m system (525 lines/60hz) pal system (625 lines/50hz) y 06399-064 figure 63. square pixel mode eav/sa v embedded timing field pixel data pal = 308 clock cycles ntsc = 236 clock cycles cb y cr y hsync 0 6399-065 figure 64. square pixel mode active pixel timing
ADV7342/adv7343 rev. 0 | page 52 of 88 filters table 39 shows an overview of the programmable filters available on the ADV7342/adv7343. table 39. selectable filters filter subaddress sd luma lpf ntsc 0x80 sd luma lpf pal 0x80 sd luma notch ntsc 0x80 sd luma notch pal 0x80 sd luma ssaf 0x80 sd luma cif 0x80 sd luma qcif 0x80 sd chroma 0.65 mhz 0x80 sd chroma 1.0 mhz 0x80 sd chroma 1.3 mhz 0x80 sd chroma 2.0 mhz 0x80 sd chroma 3.0 mhz 0x80 sd chroma cif 0x80 sd chroma qcif 0x80 sd prpb ssaf 0x82 ed/hd chroma input 0x33 ed/hd sinc compensation filter 0x33 ed/hd chroma ssaf 0x33 sd internal filter response subaddress 0x80, bits[7:2]; subaddress 0x82, bit 0 the y filter supports several different frequency responses, including two low-pass responses, two notch responses, an extended (ssaf) response with or without gain boost attenuation, a cif response, and a qcif response. the prpb filter supports several different frequency responses, including six low-pass responses, a cif response, and a qcif response, as shown in figure 39 and figure 40. if sd ssaf gain is enabled (subaddress 0x87, bit 4), there are 13 response options in the ?4 db to +4 db range. the desired response can be programmed using subaddress 0xa2. the variation of frequency responses is shown in figure 36 to figure 38. in addition to the chroma filters listed in table 39, the ADV7342/ adv7343 contain an ssaf filter specifically designed for the color difference component outputs, pr and pb. this filter has a cutoff frequency of ~2.7 mhz and a gain of C40 db at 3.8 mhz (see figure 65). this filter can be controlled with subaddress 0x82, bit 0. frequency (mhz) 0 gain (db) ?10 ?30 ?50 ?60 ?20 ?40 6 5 4 3 2 1 0 extended (ssaf) prpb filter mode 06399-066 figure 65. prpb ssaf filter if this filter is disabled, one of the chroma filters shown in table 40 can be selected and used for the cvbs or luma/ chroma signal. table 40. internal filter specifications filter pass-band ripple (db) 1 3 db bandwidth (mhz) 2 luma lpf ntsc 0.16 4.24 luma lpf pal 0.1 4.81 luma notch ntsc 0.09 2.3/4.9/6.6 luma notch pal 0.1 3.1/5.6/6.4 luma ssaf 0.04 6.45 luma cif 0.127 3.02 luma qcif monotonic 1.5 chroma 0.65 mhz monotonic 0.65 chroma 1.0 mhz monotonic 1 chroma 1.3 mhz 0.09 1.395 chroma 2.0 mhz 0.048 2.2 chroma 3.0 mhz monotonic 3.2 chroma cif monotonic 0.65 chroma qcif monotonic 0.5 1 pass-band ripple is the maximum fluctuation from the 0 db response in the pass band, measured in db. the pass band is defined to have 0 hz to fc (hz) frequency limits for a low-pass filter, and 0 hz to f1 (hz) and f2 (hz) to infinity for a notch filter, where fc, f1, and f2 are the ?3 db points. 2 3 db bandwidth refers to the ?3 db cutoff frequency.
ADV7342/adv7343 rev. 0 | page 53 of 88 ed/hd sinc compensation filter response subaddress 0x33, bit 3 the ADV7342/adv7343 include a filter designed to counter the effect of sinc roll-off in dac 1, dac 2, and dac 3 while operating in ed/hd mode. this filter is enabled by default. it can be disabled using subaddress 0x33, bit 3. the benefit of the filter is illustrated in figure 66 and figure 67. frequency (mhz) 0.5 ?0.5 30 5 0 gain (db) 10 15 20 25 0.4 0.1 ?0.2 ?0.3 ?0.4 0.3 0.2 0 ?0.1 06399-067 figure 66. ed/hd sinc compensation filter enabled frequency (mhz) 0.5 ?0.5 30 5 0 gain (db) 10 15 20 25 0.4 0.1 ?0.2 ?0.3 ?0.4 0.3 0.2 0 ?0.1 06399-068 figure 67. ed/hd sinc compensation filter disabled ed/hd test pattern color controls subaddress 0x36 to subaddress 0x38 three 8-bit registers at subaddress 0x36 to subaddress 0x38 are used to program the output color of the internal ed/hd test pattern generator (subaddress 0x31, bit 2 = 1), whether it be the lines of the cross hatch pattern or the uniform field test pattern. they are not functional as color controls for external pixel data input. the values for the luma (y) and the color difference (cr and cb) signals used to obtain white, black, and saturated primary and complementary colors conform to the itu-r bt.601-4 standard. table 41 shows sample color values that can be programmed into the color registers when the output standard selection is set to eia 770.2/eia 770.3 (subaddress 0x30, bits[1:0] = 00). table 41. sample color values for eia 770.2/eia 770.3 ed/hd output standard selection sample color y value cr value cb value white 235 (0xeb) 128 (0x80) 128 (0x80) black 16 (0x10) 128 (0x80) 128 (0x80) red 81 (0x51) 240 (0xf0) 90 (0x5a) green 145 (0x91) 34 (0x22) 54 (0x36) blue 41 (0x29) 110 (0x6e) 240 (0xf0) yellow 210 (0xd2) 146 (0x92) 16 (0x10) cyan 170 (0xaa) 16 (0x10) 166 (0xa6) magenta 106 (0x6a) 222 (0xde) 202 (0xca) color space conversion matrix subaddress 0x03 to subaddress 0x09 the internal color space conversion (csc) matrix automatically performs all color space conversions based on the input mode programmed in the mode select register (subaddress 0x01, bits[6:4]). table 42 and table 43 show the options available in this matrix. an sd color space conversion from rgb-in to yprpb-out is possible. an ed/hd color space conversion from rgb-in to yprpb-out is not possible. table 42. sd color space conversion options input output 1 yprpb/rgb out (reg. 0x02, bit 5) rgb in/ycrcb in (reg. 0x87, bit 7) ycrcb yprpb 1 0 ycrcb rgb 0 0 rgb yprpb 1 1 rgb rgb 0 1 1 cvbs/yc outputs are available for all csc combinations. table 43. ed/hd color space conversion options input output yprpb/rgb out (reg. 0x02, bit 5) rgb in/ycrcb in (reg. 0x35, bit 1) ycrcb yprpb 1 0 ycrcb rgb 0 0 rgb rgb 0 1 ed/hd manual csc matrix adjust feature the ed/hd manual csc matrix adjust feature provides custom coefficient manipulation for color space conversions and is used in ed and hd modes only. the ed/hd manual csc matrix adjust feature can be enabled using subaddress 0x02, bit 3. normally, there is no need to enable this feature because the csc matrix automatically performs the color space conversion based on the input mode chosen (ed or hd) and the input and output color spaces selected (see table 43). for this reason, the ed/hd manual csc matrix adjust feature is disabled by default.
ADV7342/adv7343 rev. 0 | page 54 of 88 if rgb output is selected, the ed/hd csc matrix scalar uses the following equations: r = gy y + rv pr g = gy y ? ( gu pb) ? ( gv pr) b = gy y + bu pb note that subtractions are implemented in hardware. if yprpb output is selected, the following equations are used: y = gy y pr = rv pr pb = bu pb where: gy = subaddress 0x05, bits[7:0] and subaddress 0x03, bits[1:0]. gu = subaddress 0x06, bits[7:0] and subaddress 0x04, bits[7:6]. gv = subaddress 0x07, bits[7:0] and subaddress 0x04, bits[5:4]. bu = subaddress 0x08, bits[7:0] and subaddress 0x04, bits[3:2]. rv = subaddress 0x09, bits[7:0] and subaddress 0x04, bits[1:0]. upon power-up, the csc matrix is programmed with the default values shown in table 44. table 44. ed/hd manual csc matrix default values subaddress default 0x03 0x03 0x04 0xf0 0x05 0x4e 0x06 0x0e 0x07 0x24 0x08 0x92 0x09 0x7c when the ed/hd manual csc matrix adjust feature is enabled, the default coefficient values in subaddress 0x03 to subaddress 0x09 are correct for the hd color space only. the color components are converted according to the following 1080i and 720p standards (smpte 274m, smpte 296m): r = y + 1.575 pr g = y ? 0.468 pr ? 0.187 pb b = y + 1.855 pb the conversion coefficients should be multiplied by 315 before being written to the ed/hd csc matrix registers this is reflected in the default values for gy = 0x13b, gu = 0x03b, gv = 0x093, bu = 0x248, and rv = 0x1f0. if the ed/hd manual csc matrix adjust feature is enabled and another input standard (such as ed) is used, the scale values for gy, gu, gv, bu, and rv must be adjusted according to this input standard color space. the user should consider that the color component conversion could use different scale values. for example, smpte 293m uses the following conversion: r = y + 1.402 pr g = y C 0.714 pr C 0.344 pb b = y + 1.773 pb the programmable csc matrix is used for external ed/hd pixel data and is not functional when internal test patterns are enabled. programming the csc matrix if custom manipulation of the ed/hd csc matrix coefficients is required for a ycrcb-to-rgb color space conversion, use the following procedure: 1. enable the ed/hd manual csc matrix adjust feature (subaddress 0x02, bit 3). 2. set the output to rgb (subaddress 0x02, bit 5). 3. disable sync on prpb (subaddress 0x35, bit 2). 4. enable sync on rgb (optional) (subaddress 0x02, bit 4). the gy value controls the green signal output level, the bu value controls the blue signal output level, and the rv value controls the red signal output level. sd luma and color control subaddress 0x9c to subaddress 0x9f sd y scale, sd cb scale, and sd cr scale are three 10-bit control registers that scale the sd y, cb, and cr output levels. each of these registers represents the value required to scale the cb or cr level from 0.0 to 2.0 times its initial value and the y level from 0.0 to 1.5 times its initial level. the value of these 10 bits is calculated using the following equation: y, cb, or cr scale value = scale factor 512 for example, if scale factor = 1.3 y, cb, or cr scale value = 1.3 512 = 665.6 y, cb, or cr scale value = 666 (rounded to the nearest integer) y, cb, or cr scale value = 1010 0110 10b subaddress 0x9c, sd scale lsb register = 0x2a subaddress 0x9d, sd y scale register = 0xa6 subaddress 0x9e, sd cb scale register = 0xa6 subaddress 0x9f, sd cr scale register = 0xa6 note that this feature affects all interlaced output signals, that is, cvbs, y/c, yprpb, and rgb.
ADV7342/adv7343 rev. 0 | page 55 of 88 sd hue adjust control subaddress 0xa0 when enabled, the sd hue adjust control register (subaddress 0xa0) is used to adjust the hue on the sd composite and chroma outputs. this feature can be enabled using subaddress 0x87, bit 2. subaddress 0xa0 contains the bits required to vary the hue of the video data, that is, the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the color burst. the ADV7342/adv7343 provide a range of 22.5 in increments of 0.17578125. for normal operation (zero adjustment), this register is set to 0x80. values 0xff and 0x00 represent the upper and lower limits, respectively, of the attainable adjustment in ntsc mode. values 0xff and 0x01 represent the upper and lower limits, respectively, of the attainable adjustment in pal mode. the hue adjust value is calculated using the following equation: hue adjust () = 0.17578125 ( hcr d ? 128) where hcr d is the hue adjust control register (decimal) for example, to adjust the hue by +4, write 0x97 to the hue adjust control register. 97 x 0 151 128 17578125 . 0 4 = + ? ? ? ? ? ? where the sum is rounded to the nearest integer. to adjust the hue by ?4, write 0x69 to the hue adjust control register. 9 6 x 0 105 128 17578125 . 0 4 = + ? ? ? ? ? ? ? where the sum is rounded to the nearest integer. sd brightness detect subaddress 0xba the ADV7342/adv7343 allow monitoring of the brightness level of the incoming video data. the sd brightness detect register (subaddress 0xba) is a read-only register. sd brightness control subaddress 0xa1, bits[6:0] when this feature is enabled, the sd brightness/wss control register (subaddress 0xa1) is used to control brightness by adding a programmable setup level onto the scaled y data. this feature can be enabled using subaddress 0x87, bit 3. for ntsc with pedestal, the setup can vary from 0 ire to 22.5 ire. for ntsc without pedestal and for pal, the setup can vary from ?7.5 ire to +15 ire. the sd brightness control register is an 8-bit register. the seven lsbs of this 8-bit register are used to control the brightness level, which can be a positive or negative value. for example, to add +20 ire brightness level to an ntsc signal with pedestal, write 0x28 to subaddress 0xa1. 0 (sd brightness value) = 0 ( ire value 2.015631) = 0 (20 2.015631) = 0 (40.31262) 0x28 to add C7 ire brightness level to a pal signal, write 0x72 to subaddress 0xa1. 0 ( sd brightness value ) = 0 ( ire value 2.075631) = 0 (7 2.015631) = 0x(14.109417) 0001110b 0001110b into twos complement = 1110010b = 0x72 table 45. sample brightness control values 1 setup level (ntsc) with pedestal setup level (ntsc) without pedestal setup level (pal) brightness control value 22.5 ire 15 ire 15 ire 0x1e 15 ire 7.5 ire 7.5 ire 0x0f 7.5 ire 0 ire 0 ire 0x00 0 ire ?7.5 ire ?7.5 ire 0x71 1 values in the range of 0x3f to 0x44 could result in an invalid output signal. sd input standard auto detection subaddress 0x87, bit 5 the ADV7342/adv7343 include an sd input standard auto- detect feature. this sd feature can be enabled by setting subaddress 0x87, bit 5 to 1. when enabled, the ADV7342/adv7343 can automatically identify an ntsc or pal b/d/g/h/i input stream. the ADV7342/adv7343 automatically update the subcarrier frequency registers with the appropriate value for the identified standard. the ADV7342/adv7343 are also configured to correctly encode the identified standard. the sd standard bits (subaddress 0x80, bits[1:0]) and the subcarrier frequency registers are not updated to reflect the identified standard. all registers retain their default or user- defined values. ntsc without pedest a l no setup value added positive setup value added 100 ire 0 ire negative setup value added ?7.5 ire +7.5 ire 06399-069 figure 68. examples of brightness control values
ADV7342/adv7343 rev. 0 | page 56 of 88 double buffering subaddress 0x33, bit 7 for ed/hd, subaddress 0x88, bit 2 for sd double-buffered registers are updated once per field. double buffering improves overall performance, because modifications to register settings are not made during active video, but take effect prior to the start of the active video on the next field. double buffering can be activated on the following ed/hd registers using subaddress 0x33, bit 7: ed/hd gamma a and gamma b curves, and ed/hd cgms registers. double buffering can be activated on the following sd registers using subaddress 0x88, bit 2: sd gamma a and gamma b curves, sd y scale, sd cr scale, sd cb scale, sd brightness, sd closed captioning, and sd macrovision bits[5:0] (subaddress 0xe0, bits[5:0]). programmable dac gain control subaddress 0x0a to subaddress 0x0b it is possible to adjust the dac output signal gain up or down from its absolute level. this is illustrated in figure 69. dac 4 to dac 6 are controlled by register 0x0a. dac 1 to dac 3 are controlled by register 0x0b. case b 700mv 300mv negative gain programmed in dac output level registers, subaddress 0x0a, 0x0b case a gain programmed in dac output level registers, subaddress 0x0a, 0x0b 700mv 300mv 0 6399-070 figure 69. programmable dac gain?positive and negative gain in case a of figure 69, the video output signal is gained. the absolute level of the sync tip and blanking level both increase with respect to the reference video output signal. the overall gain of the signal is increased from the reference signal. in case b of figure 69, the video output signal is reduced. the absolute level of the sync tip and blanking level both decrease with respect to the reference video output signal. the overall gain of the signal is reduced from the reference signal. the range of this feature is specified for 7.5% of the nominal output from the dacs. for example, if the output current of the dac is 4.33 ma, the dac gain control feature can change this output current from 4.008 ma (?7.5%) to 4.658 ma (+7.5%). the reset value of the control registers is 0x00, that is, nominal dac current is output. table 46 is an example of how the output current of the dacs varies for a nominal 4.33 ma output current. table 46. dac gain control reg. 0x0a or reg.0x0b dac current (ma) % gain note 0100 0000 (0x40) 4.658 7.5000% 0011 1111 (0x3f) 4.653 7.3820% 0011 1110 (0x3e) 4.648 7.3640% ... ... ... ... ... ... 0000 0010 (0x02) 4.43 0.0360% 0000 0001 (0x01) 4.38 0.0180% 0000 0000 (0x00) 4.33 0.0000% reset value, nominal 1111 1111 (0xff) 4.25 ?0.0180% 1111 1110 (0xfe) 4.23 ?0.0360% ... ... ... ... ... ... 1100 0010 (0xc2) 4.018 ?7.3640% 1100 0001 (0xc1) 4.013 ?7.3820% 1100 0000 (0xc0) 4.008 ?7.5000% gamma correction subaddress 0x44 to subaddress 0x57 for ed/hd, subaddress 0xa6 to subaddress 0xb9 for sd generally, gamma correction is applied to compensate for the nonlinear relationship between signal input and output brightness level (as perceived on a crt). it can also be applied wherever nonlinear processing is used. gamma correction uses the function signal out = ( signal in ) where = is the gamma correction factor. gamma correction is available for sd and ed/hd video. for both variations, there are 20, 8-bit registers. they are used to program the gamma correction curve a and gamma correction curve b. ed/hd gamma correction is enabled using subaddress 0x35, bit 5. ed/hd gamma correction curve a is programmed at subaddress 0x44 to subaddress 0x4d, and ed/hd gamma correction curve b is programmed at subaddress 0x4e to subaddress 0x57.
ADV7342/adv7343 rev. 0 | page 57 of 88 sd gamma correction is enabled using subaddress 0x88, bit 6. sd gamma correction curve a is programmed at subaddress 0xa6 to subaddress 0xaf, and sd gamma correction curve b is programmed at subaddress 0xb0 to subaddress 0xb9. gamma correction is performed on the luma data only. the user can choose one of two correction curves, curve a or curve b. only one of these curves can be used at a time. for ed/hd gamma correction, curve selection is controlled using subaddress 0x35, bit 4. for sd gamma correction, curve selection is controlled using subaddress 0x88, bit 7. the shape of the gamma correction curve is controlled by defining the curve response at 10 different locations along the curve. by altering the response at these locations, the shape of the gamma correction curve can be modified. between these points, linear interpolation is used to generate intermediate values. considering the curve has a total length of 256 points, the 10 programmable locations are at points 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. locations 0, 16, 240, and 255 are fixed and cannot be changed. from curve locations 16 to 240, the values at the programmable locations and, therefore, the response of the gamma correction curve should be calculated to produce the following result: x desired = ( x input ) where: x desired is the desired gamma corrected output. x input is the linear input signal. is the gamma correction factor. to program the gamma correction registers, calculate the 10 programmable curve values using the following formula: 16 ) 16 240 ( 16 240 16 + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = n n where: n is the value to be written into the gamma correction register for point n on the gamma correction curve. n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224. is the gamma correction factor. for example, setting = 0.5 for all programmable curve data points results in the following y n values: y 24 = [(8/224) 0.5 224] + 16 = 58 y 32 = [(16/224) 0.5 224] + 16 = 76 y 48 = [(32/224) 0.5 224] + 16 = 101 y 64 = [(48/224) 0.5 224] + 16 = 120 y 80 = [(64/224) 0.5 224] + 16 = 136 y 96 = [(80/224) 0.5 224] + 16 = 150 y 128 = [(112/224) 0.5 224] + 16 = 174 y 160 = [(144/224) 0.5 224] + 16 = 195 y 192 = [(176/224) 0.5 224] + 16 = 214 y 224 = [(208/224) 0.5 224] + 16 = 232 where the sum of each equation is rounded to the nearest integer. the gamma curves in figure 70 and figure 71 are examples only; any user-defined curve in the range from 16 to 240 is acceptable. location 0 0 50 100 150 200 250 300 50 100 150 200 250 0.5 signal input gamm a corrected amplitude signal output gamma correction block output to a ramp input 06399-071 figure 70. signal input (ramp) and signal output for gamma 0.5 location 0 0 50 100 150 200 250 300 50 100 150 200 250 gamm a corrected amplitude gamma correction block to a ramp input for various gamma values 0.3 0.5 1.5 1.8 s i g n a l i n p u t 06399-072 figure 71. signal input (ramp) and selectable output curves
ADV7342/adv7343 rev. 0 | page 58 of 88 ed/hd sharpness filter and adaptive filter controls subaddress 0x40, subaddress 0x58 to subaddress 0x5d there are three filter modes available on the ADV7342/adv7343: a sharpness filter mode and two adaptive filter modes. ed/hd sharpness filter mode to enhance or attenuate the y signal in the frequency ranges shown in figure 72, the ed/hd sharpness filter must be enabled (subaddress 0x31, bit 7) and the ed/hd adaptive filter must be disabled (subaddress 0x35, bit 7). to select one of the 256 individual responses, the corresponding gain values, which range from C8 to +7 for each filter, must be programmed into the ed/hd sharpness filter gain register at subaddress 0x40. ed/hd adaptive filter mode the ed/hd adaptive filter threshold a, b, and c registers, the ed/hd adaptive filter gain 1, 2, and 3 registers, and the ed/hd sharpness filter gain register are used in adaptive filter mode. to activate the adaptive filter control, the ed/hd sharpness filter and the ed/hd adaptive filter must be enabled (subaddress 0x31, bit 7, and subaddress 0x35, bit 7, respectively). the derivative of the incoming signal is compared to the three programmable threshold values: ed/hd adaptive filter threshold a, b, and c (subaddress 0x5b, subaddress 0x5c, and subaddress 0x5d, respectively). the recommended threshold range is 16 to 235, although any value in the range of 0 to 255 can be used. the edges can then be attenuated with the settings in the ed/hd adaptive filter gain 1, 2, and 3 registers (subaddress 0x58, subaddress 0x59, and subaddress 0x5a, respectively), and the ed/hd sharpness filter gain register (subaddress 0x40). there are two adaptive filter modes available. the mode is selected using the ed/hd adaptive filter mode control (subaddress 0x35, bit 6): ? mode a is used when the ed/hd adaptive filter mode control is set to 0. in this case, filter b (lpf) is used in the adaptive filter block. in addition, only the programmed values for gain b in the ed/hd sharpness filter gain register and ed/hd adaptive filter gain 1, 2, and 3 registers are applied when needed. the gain a values are fixed and cannot be changed. ? mode b is used when ed/hd adaptive filter mode control is set to 1. in this mode, a cascade of filter a and filter b is used. both settings for gain a and gain b in the ed/hd sharpness filter gain register and ed/hd adaptive filter gain 1, 2, and 3 registers become active when needed. frequency (mhz) filter a response (gain ka) magnitude 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 frequency (mhz) filter b response (gain kb) magnitude 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 frequency (mhz) magnitude response (linear scale) 1.0 1.1 1.2 1.3 1.4 1.5 1.6 10 12 input s ignal: step frequency response in sharpness filter mode with ka = 3 and kb = 7 sharpness and adaptive filter control block 0 2 4 6 8 06399-073 figure 72. ed/hd sharpness and adaptive filter control block
ADV7342/adv7343 rev. 0 | page 59 of 88 f e d a b c 1 r4 r2 ch1 500mv m 4.00s ch1 all fields ref a 500mv 4.00s 1 r2 r1 1 ch1 500mv m 4.00s ch1 all fields ref a 500mv 4.00s 1 9.99978ms 9.99978ms 06399-074 figure 73. ed/ hd sharpness filter control with different gain settings for ed/hd sharpness filter gain values ed/hd sharpness filter and adaptive filter application examples sharpness filter application the ed/hd sharpness filter can be used to enhance or attenuate the y video output signal. the register settings in table 47 were used to achieve the results shown in figure 73. input data was generated by an external signal source. table 47. ed/hd sharpness control subaddress register setting reference 1 0x00 0xfc 0x01 0x10 0x02 0x20 0x30 0x00 0x31 0x81 0x40 0x00 a 0x40 0x08 b 0x40 0x04 c 0x40 0x40 d 0x40 0x80 e 0x40 0x22 f 1 see figure 73. adaptive filter control application the register settings in table 48 are used to obtain the results shown in figure 75, that is, to remove the ringing on the input y signal, as shown in figure 74. input data is generated by an external signal source. table 48. register settings for figure 75 subaddress register setting 0x00 0xfc 0x01 0x38 0x02 0x20 0x30 0x00 0x31 0x81 0x35 0x80 0x40 0x00 0x58 0xac 0x59 0x9a 0x5a 0x88 0x5b 0x28 0x5c 0x3f 0x5d 0x64 06399-075 figure 74. input signal to ed/hd adaptive filter 06399-076 figure 75. output signal from ed/hd adaptive filter (mode a)
ADV7342/adv7343 rev. 0 | page 60 of 88 when changing the adaptive filter mode to mode b (subaddress 0x35, bit 6), the output shown in figure 76 can be obtained. 0 6399-077 figure 76. output signal from ed/hd adaptive filter (mode b) sd digital noise reduction subaddress 0xa3 to subaddress 0xa5 digital noise reduction (dnr) is applied to the y data only. a filter block selects the high frequency, low amplitude compo- nents of the incoming signal (dnr input select). the absolute value of the filter output is compared to a programmable threshold value (dnr threshold control). there are two dnr modes available, dnr mode and dnr sharpness mode. in dnr mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. a programmable amount (coring gain border, coring gain data) of this noise signal is subtracted from the original signal. in dnr sharpness mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise. otherwise, if the level exceeds the threshold, now identified as a valid signal, a fraction of the signal (coring gain border, coring gain data) is added to the original signal to boost high frequency components and sharpen the video image. in mpeg systems, it is common to process the video information in blocks of 8 pixels 8 pixels for mpeg2 systems, or 16 pixels 16 pixels for mpeg1 systems (block size control). dnr can be applied to the resulting block transition areas that are known to contain noise. generally, the block transition area contains two pixels. it is possible to define this area to contain four pixels (border area). it is also possible to compensate for variable block positioning or differences in ycrcb pixel timing with the use of the dnr block offset. the digital noise reduction registers are three 8-bit registers. they are used to control the dnr processing. block size control border area block offset coring gain data coring gain border gain dnr control filter output > threshold? input filter block filter output < threshold dnr out + + main signal path add signal above threshold range from original signal dnr sharpness mode noise signal path y data input block size control border area block offset coring gain data coring gain border gain dnr control filter output < threshold? input filter block filter output > threshold dnr out main signal path subtract signal in threshold range from original signal dnr mode noise signal path y dat a input ? + 06399-078 figure 77. sd dnr block diagram coring gain bordersubaddress 0xa3, bits[3:0] these four bits are assigned to the gain factor applied to border areas. in dnr mode, the range of gain values is 0 to 1 in increments of 1/8. this factor is applied to the dnr filter output that lies below the set threshold range. the result is then subtracted from the original signal. in dnr sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. this factor is applied to the dnr filter output that lies above the threshold range. the result is added to the original signal. coring gain datasubaddress 0xa3, bits[7:4] these four bits are assigned to the gain factor applied to the luma data inside the mpeg pixel block. in dnr mode, the range of gain values is 0 to 1 in increments of 1/8. this factor is applied to the dnr filter output that lies below the set threshold range. the result is then subtracted from the original signal. in dnr sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. this factor is applied to the dnr filter output that lies above the threshold range. the result is added to the original signal.
ADV7342/adv7343 rev. 0 | page 61 of 88 oxxxxxxooxxxxxxo oxxxxxxooxxxxxxo oxxxxxxooxxxxxxo dnr27 to dnr24 = 0x01 offset caused by variations in input timing apply border coring gain apply dat a coring gain 0 6399-079 figure 78. sd dnr offset control dnr thresholdsubaddress 0xa4, bits[5:0] these six bits are used to define the threshold value in the range of 0 to 63. the range is an absolute value. border areasubaddress 0xa4, bit 6 when this bit is set to logic 1, the block transition area can be defined to consist of four pixels. if this bit is set to logic 0, the border transition area consists of two pixels, where one pixel refers to two clock cycles at 27 mhz. 720 485 pixels (ntsc) 8 8 pixel block 2-pixel border data 8 8 pixel block 06399-080 figure 79. sd dnr border area block size controlsubaddress 0xa4, bit 7 this bit is used to select the size of the data blocks to be processed. setting the block size control function to logic 1 defines a 16 pixel 16 pixel data block, and logic 0 defines an 8 pixel 8 pixel data block, where one pixel refers to two clock cycles at 27 mhz. dnr input select controlsubaddress 0xa5, bits[2:0] three bits are assigned to select the filter, which is applied to the incoming y data. the signal that lies in the pass band of the selected filter is the signal that is dnr processed. figure 80 shows the filter responses selectable with this control. filter c filter b filter a filter d frequency (mhz) 0 0.2 0.4 0.6 magnitude 0.8 1.0 0 1 23 45 6 06399-081 figure 80. sd dnr input select dnr mode controlsubaddress 0xa5, bit 4 this bit controls the dnr mode selected. logic 0 selects dnr mode; logic 1 selects dnr sharpness mode. dnr works on the principle of defining low amplitude, high frequency signals as probable noise and subtracting this noise from the original signal. in dnr mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from the original signal. the threshold is set in dnr register 1. when dnr sharpness mode is enabled, it is possible to add a fraction of the signal that lies above the set threshold to the original signal, because this data is assumed to be valid data and not noise. the overall effect is that the signal is boosted (similar to using the extended ssaf filter). dnr block offset controlsubaddress 0xa5, bits[7:4] four bits are assigned to this control, which allows a shift of the data block of 15 pixels maximum. consider the coring gain positions fixed. the block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data. sd active video edge control subaddress 0x82, bit 7 the ADV7342/adv7343 are able to control fast rising and falling signals at the start and end of active video in order to minimize ringing. when the active video edge control feature is enabled (subaddress 0x82, bit 7 = 1), the first three pixels and the last three pixels of the active video on the luma channel are scaled so that maximum transitions on these pixels are not possible. at the start of active video, the first three pixels are multiplied by 1/8, 1/2, and 7/8, respectively. approaching the end of active video, the last three pixels are multiplied by 7/8, 1/2, and 1/8, respectively. all other active video pixels pass through unprocessed.
ADV7342/adv7343 rev. 0 | page 62 of 88 100 ire 0 ire 100 ire 12.5 ire 87.5 ire 0 ire 50 ire lum a channel with active video edge disabled lum a channel with active video edge enabled 06399-082 figure 81. example of active video edge functionality volts 024 f2 l135 681012 ire:flt ?50 0 0 50 100 0.5 06399-083 figure 82. example of video output with subaddress 0x82, bit 7 = 0 volts 02 ?2 4 6 8 10 12 f2 l135 ire:flt ?50 0 50 100 0 0.5 06399-084 figure 83. example of video output with subaddress 0x82, bit 7 = 1
ADV7342/adv7343 rev. 0 | page 63 of 88 external horizontal and vertical synchronization control for timing synchronization purposes, the ADV7342/adv7343 are able to accept either eav/sav time codes embedded in the input pixel data or external synchronization signals provided on the s_hsync , s_vsync , p_hsync , p_vsync , and p_blank pins (see table 49). it is also possible to output synchronization signals on the s_hsync and s_vsync pins (see table 50 to table 52). table 49. timing synchronization signal input options signal pin condition sd hsync in s_hsync sd slave timing mode 1, 2, or 3 selected (subaddress 0x8a[2:0]). 1 sd vsync /field in s_vsync sd slave timing mode 1, 2, or 3 selected (subaddress 0x8a[2:0]). 1 ed/hd hsync in p_hsync ed/hd timing synchronization inputs enabled (subaddress 0x30, bit 2 = 0). ed/hd vsync /field in p_vsync ed/hd timing synchronization inputs enabled (subaddress 0x30, bit 2 = 0). ed/hd blank in p_blank 1 sd and ed/hd timing synchronization outputs must also be disabled (subaddress 0x02[7:6] = 00). table 50. timing synchronization signal output options signal pin condition sd hsync out s_hsync sd timing synchronization outputs en abled (subaddress 0x02, bit 6 = 1). 1 sd vsync /field out s_vsync sd timing synchronization outputs en abled (subaddress 0x02, bit 6 = 1). 1 ed/hd hsync out s_hsync ed/hd timing synchronization outputs enabled (subaddress 0x02, bit 7 = 1). ed/hd vsync /field out s_vsync ed/hd timing synchronization outputs enabled (subaddress 0x02, bit 7 = 1). 1 ed/hd timing synchronization outputs must also be disabled (subaddress 0x02, bit 7 = 0). table 51. s_hsync output control 1 ed/hd input sync format (0x30, bit 2) ed/hd hsync control (0x34, bit 1) ed/hd sync output enable (0x02, bit 7) sd sync output enable (0x02, bit 6) signal on s_hsync pin duration x x 0 0 tristate. C x x 0 1 pipelined sd hsync . see appendix 5 sd timing . 0 0 1 x pipelined ed/hd hsync . as per hsync timing. 1 0 1 x pipelined ed/hd hsync based on av code h bit. same as line blanking interval. x 1 1 x pipelined ed/hd hsync based on horizontal counter. same as embedded hsync . 1 in all ed/hd standards where there is an hsync output, the start of the hsync pulse is aligned with the falling edge of the embedded hsync in the output video. table 52. s_vsync output control 1 ed/hd input sync format (0x30, bit 2) ed/hd vsync control (0x34, bit 2) ed/hd sync output enable (0x02, bit 7) sd sync output enable (0x02, bit 6) video standard signal on s_vsync pin duration x x 0 0 x tristate. C x x 0 1 interlaced pipelined sd vsync /field. see appendix 5sd timing . 0 0 1 x x pipelined ed/hd vsync or field signal. as per vsync or field signal timing. 1 0 1 x all hd interlaced standards pipelined field signal based on av code f bit. field. 1 0 1 x all ed/hd progressive standards pipelined vsync based on av code v bit. vertical blanking interval. x 1 1 x all ed/hd standards except 525p pipelined ed/hd vsync based on vertical counter. aligned with serration lines. x 1 1 x 525p pipelined ed/hd vsync based on vertical counter. vertical blanking interval. 1 in all ed/hd standards where there is a vsync output, the start of the vsync pulse is aligned with the falling edge of the embedded vsync in the output video.
ADV7342/adv7343 rev. 0 | page 64 of 88 low power mode subaddress 0x0d, bits[2:0] for power sensitive applications, the ADV7342/adv7343 support an analog devices, inc. proprietary low power mode of operation on dac 1, dac 2, and dac 3. to utilize this low power mode, these dacs must be operating in full-drive mode (r set = 510 , r l = 37.5 ). low power mode is not available in low drive mode (r set = 4.12 k, r l = 300 ). low power mode can be independently enabled or disabled on dac 1, dac 2, and dac 3 using subaddress 0x0d, bits[2:0]. low power mode is disabled by default on each dac. in low power mode, dac current consumption is content dependent. on a typical video stream, it can be reduced by as much as 40%. for applications requiring the highest possible video performance, low power mode should be disabled. cable detection subaddress 0x10 the ADV7342/adv7343 include an analog devices, inc. proprietary cable detection feature. the cable detection feature is available on dac 1 and dac 2, while operating in full-drive mode (r set1 = 510 , r l1 = 37.5 , assuming a connected cable). the feature is not available in low drive mode (r set = 4.12 k, r l = 300 ). for a dac to be monitored, the dac must be powered up in subaddress 0x00. the cable detection feature can be used with all sd, ed, and hd video standards. it is available for all output configurations, that is, cvbs, yc, yprpb, and rgb output configurations. for cvbs/yc output configurations, both dac 1 and dac 2 are monitored, that is, the cvbs and yc luma outputs are monitored. for yprpb and rgb output configurations, only dac 1 is monitored, that is, the luma or green output is monitored. once per frame, the ADV7342/adv7343 monitor dac 1 and/or dac 2, updating subaddress 0x10, bit 0 and bit 1, respectively. if a cable is detected on one of the dacs, the relevant bit is set to 0. if not, the bit is set to 1. dac auto power-down subaddress 0x10, bit 4 for power sensitive applications, a dac auto power-down feature can be enabled using subaddress 0x10, bit 4. this feature is only available when the cable detection feature is enabled. with this feature enabled, the cable detection circuitry monitors dac 1 and/or dac 2 once per frame. if they are unconnected, some or all of the dacs automatically power down. which dac or dacs are powered down depends on the selected output configuration. for cvbs/yc output configurations, if dac 1 is unconnected, only dac 1 powers down. if dac 2 is unconnected, dac 2 and dac 3 power down. for yprpb and rgb output configurations, if dac 1 is unconnected, all three dacs power down. dac 2 is not monitored for yprpb and rgb output configurations. once per frame, dac 1 and/or dac 2 are monitored. if a cable is detected, the appropriate dac or dacs remain powered up for the duration of the frame. if no cable is detected, the appropriate dac or dacs power down until the next frame, when the process is repeated. pixel and control port readback subaddress 0x12 to subadd ress 0x14, subaddress 0x16 the ADV7342/adv7343 support the readback of most digital inputs via the i 2 c/spi mpu port. this feature is useful for board level connectivity testing with upstream devices. the pixel port (s[7:0], y[7:0], and c[7:0]), the control port ( s_hsync , s_vsync , p_hsync , p_vsync and p_blank ), and the sfl/miso pin are available for readback via the mpu port. the readback registers are located at subaddress 0x12 to subaddress 0x14 and subaddress 0x16. when using this feature, a clock signal should be applied to the clkin_a pin to register the levels applied to the input pins. reset mechanism subaddress 0x17, bit 1 the ADV7342/adv7343 have a software reset accessible via the i 2 c/spi mpu port. a software reset is activated by writing a 1 to subaddress 0x17, bit 1. this resets all registers to their default values. this bit is self-clearing, that is, after a 1 has been written to the bit, the bit automatically returns to 0. when operating in spi mode, a software reset does not cause the device to revert to i 2 c mode. for this to occur, the ADV7342/adv7343 need to be powered down. the ADV7342/adv7343 include a power-on reset (por) circuit to ensure correct operation after power-up.
ADV7342/adv7343 rev. 0 | page 65 of 88 printed circuit board layout and design dac configurations the ADV7342/adv7343 contain six dacs. all six dacs can be configured to operate in low drive mode. low drive mode is defined as 4.33 ma full-scale current into a 300 load, r l . dac 1, dac 2, and dac 3 can also be configured to operate in full-drive mode. full-drive mode is defined as 34.7 ma full- scale current into a 37.5 load, r l . full-drive is the recommended mode of operation for dac 1, dac 2, and dac 3. the ADV7342/adv7343 contain two r set pins. a resistor connected between the r set1 pin and agnd is used to control the full-scale output current and, therefore, the dac output voltage levels of dac 1, dac 2, and dac 3. for low drive operation, r set1 must have a value of 4.12 k, and r l must have a value of 300 . for full-drive operation, r set1 must have a value of 510 , and r l must have a value of 37.5 . a resistor connected between the r set2 pin and agnd is used to control the full-scale output current and, therefore, the dac output voltage levels of dac 4, dac 5, and dac 6. r set2 must have a value of 4.12 k, and r l must have a value of 300 (that is, low drive operation only). the resistors connected to the r set1 and r set2 pins should have a 1% tolerance. the ADV7342/adv7343 contain two compensation pins, comp1 and comp2. a 2.2 nf compensation capacitor should be connected from each of these pins to v aa . voltage reference the ADV7342/adv7343 contain an on-chip voltage reference that can be used as a board-level voltage reference via the v ref pin. alternatively, the ADV7342/adv7343 can be used with an external voltage reference by connecting the reference source to the v ref pin. for optimal performance, an external voltage reference such as the ad1580 should be used with the ADV7342/ adv7343. if an external voltage reference is not used, a 0.1 f capacitor should be connected from the v ref pin to v aa . video output buffer and optional output filter an output buffer is necessary on any dac that operates in low drive mode (r set = 4.12 k, r l = 300 ). analog devices, inc. produces a range of op amps suitable for this application, for example, the ad8061. for more information about line driver buffering circuits, see the relevant op amp data sheet. an optional reconstruction (anti-imaging) low-pass filter (lpf) may be required on the ADV7342/adv7343 dac outputs if the ADV7342/adv7343 are connected to a device that requires this filtering. the filter specifications vary with the application. the use of 16 (sd), 8 (ed), or 4 (hd) oversampling can remove the requirement for a reconstruction filter altogether. for applications requiring an output buffer and reconstruction filter, the ada4430-1 , ada4411-3 , and ada4410-6 integrated video filter buffers should be considered. table 53. ADV7342/adv7343 output rates input mode (0x01, bits[6:4]) pll control (0x00, bit 1) output rate (mhz) off 27 (2x) sd only on 216 (16x) off 27 (1x) ed only on 216 (8x) off 74.25 (1x) hd only on 297 (4x) table 54. output filter requirements application oversampling cutoff frequency (mhz) attenuation C50 db @ (mhz) sd 2 >6.5 20.5 sd 16 >6.5 209.5 ed 1 >12.5 14.5 ed 8 >12.5 203.5 hd 1 >30 44.25 hd 4 >30 267 560 ? 600 ? 22pf 600 ? dac output 75 ? bnc output 10h 560 ? 3 4 1 06399-085 figure 84. example of output filter for sd, 16 oversampling 560 ? 6.8pf 600 ? 6.8pf 600 ? dac output 75 ? bnc output 4.7h 560 ? 3 4 1 06399-086 figure 85. example of output filter for ed, 8 oversampling dac output 390nh 33pf 33pf 75 ? 500 ? 300 ? 75 ? bnc output 500 ? 3 4 1 3 4 1 0 6399-087 figure 86. example of output fi lter for hd, 4 oversampling
ADV7342/adv7343 rev. 0 | page 66 of 88 0 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?30 ?60 ?90 ?120 ?150 ?180 ?210 ?240 1m 10m 100m frequency (hz) circuit frequency response 1g group delay (seconds) phase (degrees) magnitude (db) 21n 18n 15n 12n 9n 6n 3n 0 24n gain (db) 06399-088 figure 87. output filter pl ot for sd, 16 oversampling 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 1m 10m 100m 1g frequency (hz) circuit frequency response magnitude (db) group delay (seconds) phase (degrees) gain (db) 320 240 160 80 0 ?80 ?160 ?240 480 400 14n 12n 10n 8n 6n 4n 2n 0 18n 16n 06399-089 figure 88. output filter pl ot for ed, 8 oversampling 0 ?50 1 frequency (mhz) circuit frequency response gain (db) phase (degrees) 10 100 ?10 ?20 ?30 ?40 200 ?200 120 40 ?40 ?120 group delay (seconds) phase (degrees) magnitude (db) 06399-090 figure 89. output filter pl ot for hd, 4 oversampling printed circuit board (pcb) layout the ADV7342/adv7343 are highly integrated circuits containing both precision analog and high speed digital circuitry. they have been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. it is imperative that these same design and layout techniques be applied to the system-level design so that optimal performance is achieved. the layout should be optimized for lowest noise on the ADV7342/adv7343 power and ground planes by shielding the digital inputs and providing good power supply decoupling. it is recommended to use a 4-layer printed circuit board with ground and power planes separating the signal trace layer and the solder side layer. component placement component placement should be carefully considered to separate noisy circuits, such as clock signals and high speed digital circuitry from analog circuitry. the external loop filter components and components connected to the comp, v ref , and r set pins should be placed as close as possible to and on the same side of the pcb as the ADV7342/ adv7343. adding vias to the pcb to get the components closer to the ADV7342/adv7343 are not recommended. it is recommended that the ADV7342/adv7343 be placed as close as possible to the output connector, with the dac output traces as short as possible. the termination resistors on the dac output traces should be placed as close as possible to and on the same side of the pcb as the ADV7342/adv7343. the termination resistors should overlay the pcb ground plane. external filter and buffer components connected to the dac outputs should be placed as close as possible to the ADV7342/ adv7343 to minimize the possibility of noise pickup from neighboring circuitry, and to minimize the effect of trace capacitance on output bandwidth. this is particularly important when operating in low drive mode (r set = 4.12 k, r l = 300 ). power supplies it is recommended that a separate regulated supply be provided for each power domain (v aa , v dd , v dd_io , and pv dd ). for optimal performance, linear regulators rather than switch mode regulators should be used. if switch mode regulators must be used, care must be taken with regard to the quality of the output voltage in terms of ripple and noise. this is particularly true for the v aa and pv dd power domains. each power supply should be individually connected to the system power supply at a single point through a suitable filtering device, such as a ferrite bead.
ADV7342/adv7343 rev. 0 | page 67 of 88 power supply decoupling it is recommended that each power supply pin be decoupled with 10 nf and 0.1 f ceramic capacitors. the v aa , pv dd , v dd_io , and both v dd pins should be individually decoupled to ground. the decoupling capacitors should be placed as close as possible to the ADV7342/adv7343 with the capacitor leads kept as short as possible to minimize lead inductance. a 1 f tantalum capacitor is recommended across the v aa supply in addition to the 10 nf and 0.1 f ceramic capacitors. power supply sequencing the ADV7342/adv7343 are robust to all power supply sequencing combinations. any particular sequence can be used. digital signal interconnect the digital signal traces should be isolated as much as possible from the analog outputs and other analog circuitry. digital signal traces should not overlay the v aa or pv dd power planes. due to the high clock rates used, avoid long clock traces to the ADV7342/adv7343 to minimize noise pickup. any pull-up termination resistors for the digital inputs should be connected to the v dd power supply. any unused digital inputs should be tied to ground. analog signal interconnect dac output traces should be treated as transmission lines with appropriate measures taken to ensure optimal performance (for example, impedance matched traces). the dac output traces should be kept as short as possible. the termination resistors on the dac output traces should be placed as close as possible to and on the same side of the pcb as the ADV7342/adv7343. to avoid crosstalk between the dac outputs, it is recom- mended that as much space as possible be left between the traces connected to the dac output pins. adding ground traces between the dac output traces is also recommended.
ADV7342/adv7343 rev. 0 | page 68 of 88 typical application circuit y0 y1 y2 y3 y4 y5 y6 y7 s0 s1 s2 s3 s4 s5 s6 s7 dgnd pgnd dgnd pgnd 0.1f gnd_io 0.01f gnd_io 33f gnd_io 10f gnd_io ferrite bead v dd_io v dd_io power supply decoupling 0.1f pgnd 0.01f pgnd 33f pgnd 10f pgnd ferrite bead pv dd (1.8v) pv dd power supply decoupling 0.1f agnd 0.01f agnd 33f agnd 10f agnd ferrite bead v aa v aa power supply decoupling 0.1f dgnd 0.01f dgnd 33f agnd 10f dgnd ferrite bead v dd (1.8v) v dd power supply decoupling for each power pin v dd_io pv dd v aa v dd ADV7342/adv7343 1.235v c0 c1 c2 c3 c4 c5 test0 test1 test2 test3 test4 test5 c6 c7 s_hsync s_vsync p_hsync p_vsync p_blank clkin_a clkin_b agnd agnd dgnd dgnd gnd_io gnd_io v ref ad1580 v aa 1.1k ? optional. if the internal voltage reference is used, a 0.1f capacitor should be connected from v ref to v aa . 0.1f r set1 r set2 agnd 4.12k ? 510 ? 75 ? dac 4 agnd 300 ? 510 ? agnd 510 ? + ? +v ?v dac 4 dac 5 dac 5 dac 6 dac 6 comp1 comp2 v aa 2.2nf v aa 2.2nf ext_lf2 ext_lf1 12nf 150nf 170 ? pv dd sda/sclk scl/mosi sfl/miso alsb/spi_ss pixel port inputs control inputs/outputs unused connect to dgnd clock inputs mpu port inputs/outputs dac 1 dac 2 dac 3 dac 1 dac 3 dgnd v dd dacs 1-3 low drive option r set1 agnd 4.12k ? external loop filters loop filter components s hould be located c lose to the ext_lf pins and on the same s ide of the pcb as the a dv7342/adv7343. optional lpf agnd notes 1. for optimum performance, external components connected to the comp, r set , v ref and dac output pins should be located close to and on the same side of the pcb as the ADV7342/adv7343 . 2. when operating in i 2 c mode, the i 2 c device address is configurable using the alsb/spi_ss pin: alsb/spi_ss = 0, i 2 c device address = 0xd4 or 0x54 alsb/spi_ss = 1, i 2 c device address = 0xd6 or 0x56 3. the resistors connected to the r set pins should have a 1% tolerance. ad8061 75 ? agnd 300 ? 510 ? agnd 510 ? + ? +v ?v optional lpf ad8061 75 ? agnd 300 ? 510 ? agnd 510 ? + ? +v ?v optional lpf ad8061 75 ? agnd 300 ? 510 ? agnd 510 ? + ? +v ?v optional lpf ad8061 75 ? agnd 300 ? 510 ? agnd 510 ? + ? +v ?v optional lpf ad8061 75 ? agnd 300 ? 510 ? agnd 510 ? + ? +v ?v optional lpf ad8061 dac 2 12nf 150nf 170 ? 1f agnd dac 1 dac 2 dac 3 agnd 75 ? agnd 75 ? agnd 75 ? dac 1 dac 2 dac 3 dacs 1-3 full drive option optional lpf optional lpf optional lpf 06399-091 figure 90. ADV7342/adv7343 typical application circuit
ADV7342/adv7343 rev. 0 | page 69 of 88 appendix 1copy generation management system sd cgms subaddress 0x99 to subaddress 0x9b the ADV7342/adv7343 support copy generation management system (cgms) conforming to the eiaj cpr-1204 and arib tr-b15 standards. cgms data is transmitted on line 20 of the odd fields and line 283 of even fields. subaddress 0x99, bits[6:5] control whether cgms data is output on odd or even fields or both. sd cgms data can only be transmitted when the ADV7342/ adv7343 are configured in ntsc mode. the cgms data is 20 bits long. the cgms data is preceded by a reference pulse of the same amplitude and duration as a cgms bit (see figure 91). ed cgms subaddress 0x41 to subaddress 0x43 subaddress 0x5e to subaddress 0x6e 525p the ADV7342/adv7343 support copy generation management system (cgms) in 525p mode in accordance with eiaj cpr- 1204-1. when ed cgms is enabled (subaddress 0x32, bit 6 = 1), 525p cgms data is inserted on line 41. the 525p cgms data registers are at subaddress 0x41, subaddress 0x42, and subaddress 0x43. the ADV7342/adv7343 also support cgms type b packets in 525p mode in accordance with cea-805-a. when ed cgms type b is enabled (subaddress 0x5e, bit 0 = 1), 525p cgms type b data is inserted on line 40. the 525p cgms type b data registers are at subaddress 0x5e to subaddress 0x6e. 625p the ADV7342/adv7343 support copy generation management system (cgms) in 625p mode in accordance with iec62375 (2004). when ed cgms is enabled (subaddress 0x32, bit 6 = 1), 625p cgms data is inserted on line 43. the 625p cgms data registers are at subaddress 0x42 and subaddress 0x43. hd cgms subaddress 0x41 to subaddress 0x43 subaddress 0x5e to subaddress 0x6e the ADV7342/adv7343 support copy generation management system (cgms) in hd mode (720p and 1080i) in accordance with eiaj cpr-1204-2. when hd cgms is enabled (subaddress 0x32, bit 6 = 1), 720p cgms data is applied to line 24 of the luminance vertical blanking interval. when hd cgms is enabled (subaddress 0x32, bit 6 = 1), 1080i cgms data is applied to line 19 and line 582 of the luminance vertical blanking interval. the hd cgms data registers are at subaddress 0x41, subaddress 0x42, and subaddress 0x43. the ADV7342/adv7343 also support cgms type b packets in hd mode (720p and 1080i) in accordance with cea-805-a. when hd cgms type b is enabled (subaddress 0x5e, bit 0 = 1), 720p cgms data is applied to line 23 of the luminance vertical blanking interval. when hd cgms type b is enabled (subaddress 0x5e, bit 0 = 1), 1080i cgms data is applied to line 18 and line 581 of the luminance vertical blanking interval. the hd cgms type b data registers are at subaddress 0x5e to subaddress 0x6e. cgms crc functionality if sd cgms crc (subaddress 0x99, bit 4) or ed/hd cgms crc (subaddress 0x32, bit 7) is enabled, the upper six cgms data bits, c19 to c14, which comprise the 6-bit crc check sequence, are automatically calculated on the ADV7342/adv7343. this calculation is based on the lower 14 bits (c13 to c0) of the data in the cgms data registers and the result is output with the remaining 14 bits to form the complete 20 bits of the cgms data. the calculation of the crc sequence is based on the polynomial x 6 + x + 1 with a preset value of 111111. if sd cgms crc or ed/hd cgms crc are disabled, all 20 bits (c19 to c0) are output directly from the cgms registers (crc must be calculated by the user manually). if ed/hd cgms type b crc (subaddress 0x5e, bit 1) is enabled, the upper six cgms type b data bits (p122 to p127) that comprise the 6-bit crc check sequence are automatically calculated on the ADV7342/adv7343. this calculation is based on the lower 128 bits (h0 to h5 and p0 to p121) of the data in the cgms type b data registers. the result is output with the remaining 128 bits to form the complete 134 bits of the cgms type b data. the calculation of the crc sequence is based on the polynomial x 6 + x + 1 with a preset value of 111111. if ed/hd cgms type b crc is disabled, all 134 bits (h0 to h5 and p0 to p127) are output directly from the cgms type b registers (crc must be calculated by the user manually).
ADV7342/adv7343 rev. 0 | page 70 of 88 crc sequence ref 0 ire ?40 ire +70 ire +100 ire 11.2s 2.235s 20ns 49.1s 0.5s c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 06399-092 figure 91. standard definition cgms waveform c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 crc sequence ref 5.8s 0.15s 6t 0mv ?300mv 70% 10% t = 1/( f h 33) = 963ns f h = horizontal scan frequency t 30ns +700mv 21.2s 0.22s 22t c13 c14 c15 c16 c17 c18 c19 bit 1 bit 2 06399-093 bit 20 figure 92. enhanced definition (525p) cgms waveform r s c0 lsb c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 msb peak white sync level 500mv 25mv 5.5s 0.125s r = run-in s = start code 13.7s 06399-094 figure 93. enhanced definition (625p) cgms waveform crc sequence ref 4t 3.128s 90ns 17.2s 160ns 22t t = 1/( f h 1650/58) = 781.93ns f h = horizontal scan frequency 1h t 30ns 0mv ?300mv 70% 10% +700mv c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 bit 1 bit 2 0 6399-095 bit 20 figure 94. high definition (720p) cgms waveform
ADV7342/adv7343 rev. 0 | page 71 of 88 crc sequence ref 4t 4.15s 60ns 22.84s 210ns 22t t = 1/(f h 2200/77) = 1.038s f h = horizontal scan frequency 1h t 30ns 0mv ?300mv 70% 10% +700mv c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 bit 1 bit 2 06399-096 bit 20 figure 95. high definition (1080i) cgms waveform bit 1 bit 2 h0 h1 h2 h3 h4 h5 p0 p1 p2 p3 p4 crc sequence 0mv ?300mv +700mv . p122 p123 p124 p125 p126 p127 start . . 70% 10 % notes 1. please refer to the cea-805-a specification for timing information. 06399-097 bit 134 figure 96. enhanced definition (525p) cgms type b waveform 0mv ?300mv +700mv 70% 10 % notes 1. please refer to the cea-805-a specification for timing information. bit 1 bit 2 h0 h1 h2 h3 h4 h5 p0 p1 p2 p3 p4 crc sequence . p122 p123 p124 p125 p126 p127 . . start 06399-098 bit 134 figure 97. high definition (720p and 1080i) cgms type b waveform
ADV7342/adv7343 rev. 0 | page 72 of 88 appendix 2sd wide screen signaling subaddress 0x99, subaddress 0x9a, subaddress 0x9b the ADV7342/adv7343 support wide screen signaling (wss) conforming to the etsi 300 294 standard. wss data is transmitted on line 23. wss data can be transmitted only when the device is configured in pal mode. the wss data is 14 bits long. the function of each of these bits is shown in table 55. the wss data is preceded by a run-in sequence and a start code (see figure 98). the latter portion of line 23 (after 42.5 s from the falling edge of hsync ) is available for the insertion of video. wss data transmission on line 23 can be enabled using subaddress 0x99, bit 7. it is possible to blank the wss portion of line 23 with subaddress 0xa1, bit 7. table 55. function of wss bit number bit description 13 12 11 10 9 8 7 6 5 4 3 2 1 0 setting 1 0 0 0 4:3, full format, n/a 0 0 0 1 14:9, letterbox, center 0 0 1 0 14:9, letterbox, top 1 0 1 1 16:9, letterbox, center 0 1 0 0 16:9, letterbox, top 1 1 0 1 >16:9, letterbox, center 1 1 1 0 14:9, full format, center aspect ratio, format, position 0 1 1 1 16:0, n/a, n/a 0 camera mode mode 1 film mode 0 normal pal color encoding 1 motion adaptive colorplus 0 not present helper signals 1 present reserved 0 0 no teletext subtitles 1 yes 0 0 no 0 1 subtitles in active image area 1 0 subtitles out of active image area open subtitles 1 1 reserved 0 no surround sound 1 yes 0 no copyright asserted or unknown copyright 1 copyright asserted 0 copying not restricted copy protection 1 copying restricted active video run-in sequence start code 500m v 11.0s 38.4s 42.5s w0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 06399-099 figure 98. wss waveform diagram
ADV7342/adv7343 rev. 0 | page 73 of 88 appendix 3sd closed captioning subaddress 0x91 to subaddress 0x94 the ADV7342/adv7343 support closed captioning conforming to the standard television synchronizing waveform for color transmission. closed captioning is transmitted during the blanked active line time of line 21 of the odd fields and line 284 of the even fields. closed captioning consists of a 7-cycle sinusoidal burst that is frequency- and phase-locked to the caption data. after the clock run-in signal, the blanking level is held for two data bits and is followed by the logic 1 start bit. sixteen bits of data follow the start bit. these consist of two 8-bit bytes, seven data bits, and one odd parity bit. the data for these bytes is stored in the sd closed captioning registers (subaddress 0x93 to subaddress 0x94). the ADV7342/adv7343 also support the extended closed captioning operation, which is active during even fields and encoded on scan line 284. the data for this operation is stored in the sd closed captioning registers (subaddress 0x91 to subaddress 0x92). the ADV7342/adv7343 automatically generate all clock run- in signals and timing that support closed captioning on line 21 and line 284. all pixels inputs are ignored on line 21 and line 284 if closed captioning is enabled. the fcc code of federal regulations (cfr) 47 section 15.119 and eia608 describe the closed captioning information for line 21 and line 284. the ADV7342/adv7343 use a single buffering method. this means that the closed captioning buffer is only 1-byte deep. therefore, there is no frame delay in outputting the closed captioning data, unlike other 2-byte deep buffering systems. the data must be loaded one line before it is output on line 21 and line 284. a typical implementation of this method is to use vsync to interrupt a microprocessor, which in turn loads the new data (2 bytes) in every field. if no new data is required for transmission, 0s must be inserted in both data registers; this is called nulling. it is also important to load control codes, all of which are double bytes, on line 21. otherwise, a tv does not recognize them. if there is a message such as hello world that has an odd number of characters, it is important to add a blank character at the end to make sure that the end-of-caption, 2-byte control code lands in the same field. d0 to d6 d0 to d6 10.5 0.25s 12.91s 7 cycles of 0.5035mhz clock run-in reference color burst (9 cycles) frequency = f sc = 3.579545mhz amplitude = 40 ire 50 ire 40 ire 10.003s 27.382s 33.764s byte 1 byte 0 two 7-bit + parity ascii characters (data) s t a r t p a r i t y p a r i t y 06399-100 figure 99. sd closed ca ptioning waveform, ntsc
ADV7342/adv7343 rev. 0 | page 74 of 88 appendix 4internal test pattern generation sd test patterns the ADV7342/adv7343 are able to generate sd color bar and black bar test patterns. the register settings in table 56 are used to generate an sd ntsc 75% color bar test pattern. cvbs output is available on dac 4, s-video (y/c) output is on dac 5 and dac 6, and yprpb output is on dac 1 to dac 3. upon power-up, the subcarrier frequency registers default to the appropriate values for ntsc. all other registers are set as normal/default. table 56. sd ntsc color bar test pattern register writes subaddress setting 0x00 0xfc 0x82 0xc9 0x84 0x40 to generate an sd ntsc black bar test pattern, the same settings shown in table 56 should be used with an additional write of 0x24 to subaddress 0x02. for pal output of either test pattern, the same settings are used, except that subaddress 0x80 is programmed to 0x11 and the subcarrier frequency registers are programmed as shown in table 57. table 57. pal f sc register writes subaddress description setting 0x8c f sc 0 0xcb 0x8d f sc 1 0x8a 0x8e f sc 2 0x09 0x8f f sc 3 0x2a note that when programming the f sc registers, the user must write the values in the sequence f sc 0, f sc 1, f sc 2, f sc 3. the full f sc value to be written is accepted only after the f sc 3 write is complete. ed/hd test patterns the ADV7342/adv7343 are able to generate ed/hd color bar, black bar, and hatch test patterns. the register settings in table 58 are used to generate an ed 525p hatch test pattern. yprpb output is available on dac 1 to dac 3. all other registers are set as normal/default. table 58. ed 525p hatch test pattern register writes subaddress setting 0x00 0x1c 0x01 0x10 0x31 0x05 to generate an ed 525p black bar test pattern, the same settings as shown in table 58 should be used with an additional write of 0x24 to subaddress 0x02. to generate an ed 525p flat field test pattern, the same settings shown in table 58 should be used, except that 0x0d should be written to subaddress 0x31. the y, cr, and cb levels for the hatch and flat field test patterns can be controlled using subaddress 0x36, subaddress 0x37, and subaddress 0x38, respectively. for ed/hd standards other than 525p, the same settings as shown in table 58 (and subsequent comments) are used except that subaddress 0x30, bits[7:3] are updated as appropriate.
ADV7342/adv7343 rev. 0 | page 75 of 88 appendix 5sd timing mode 0 (ccir-656)slave option (subaddress 0x8a = x x x x x 0 0 0) the ADV7342/adv7343 are controlled by the sav (start of active vide o) and eav (end of active video) time codes embedded in the pixel data. all timing information is transmitted using a 4-byte synchronization pattern. a synchronization pattern is sent imm ediately before and after each line during active picture and retrace. if the s_vsync and s_hsync pins are not used, they should be tied high during this mode. y c r y f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 f f 0 0 f f a b a b a b 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r c b y c b y c r eav code sav code ancillary data (hanc) 4 clock 4 clock 268 clock 1440 clock 4 clock 4 clock 280 clock 1440 clock end of active video line start of active video line analog video input pixels ntsc/pal m system (525 lines/60hz) pal system (625 lines/50hz) y 0 6399-101 figure 100. sd slave mode 0 mode 0 (ccir-656)master option (subaddress 0x8a = x x x x x 0 0 1) the ADV7342/adv7343 generate h and f signals required for the sa v and eav time codes in the ccir656 standard. the h bit is output on s_hsync and the f bit is output on s_vsync . 522 523 524 525 8 9 10 11 20 21 22 displ a y display vertical blank odd field even field h f 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank h f 7 6 5 4 3 2 1 06399-102 figure 101. sd master mode 0, ntsc
ADV7342/adv7343 rev. 0 | page 76 of 88 622 623 624 625 21 22 23 displ a y displ a y vertical blank h f odd field even field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 display display vertical blank h f odd field even field 313 7 6 5 4 3 2 1 0 6399-103 figure 102. sd master mode 0, pal a nalog video h f 06399-104 figure 103. sd master mode 0, data transitions mode 1slave option (subaddress 0x8a = x x x x x 0 1 0) in this mode, the ADV7342/adv7343 accept horizont al sync and odd/even field signals. when hsync is low, a transition of the field input indicates a new frame, that is, vertical retrace. the ADV7342/adv7343 automatically blank all normally blank lines as per ccir- 624. hsync and field are input on the s_hsync and s_vsync pins, respectively. 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank 522 523 524 525 59 10 11 20 21 22 displ a y displ a y vertical blank odd field even field field field hsync hsync 7 6 4 3 2 1 8 06399-105 figure 104. sd slave mode 1, ntsc
ADV7342/adv7343 rev. 0 | page 77 of 88 622 623 624 625 21 22 23 display vertical blank odd field even field field displ a y 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field display 320 field 5 7 6 4 3 2 1 hsync hsync 0 6399-106 figure 105. sd slave mode 1, pal mode 1master option (subadd ress 0x8a = x x x x x 0 1 1) in this mode, the ADV7342/adv7343 can generate hori zontal sync and odd/even field signals. when hsync is low, a transition of the field input indicates a new frame, that is, vertical retrace. the ADV7342/adv7343 automatically blank all normally blank lines as per ccir-624. pixel data is latched on the rising cloc k edge following the timing signal transitions. hsync and field are output on the s_hsync and s_vsync pins, respectively. field pixel data cb y cr y hsync pal = 132 clock/2 ntsc = 122 clock/2 06399-107 figure 106. sd timing mode 1, odd/even field transitions (master/slave) mode 2 slave option (subaddress 0x8a = x x x x x 1 0 0) in this mode, the ADV7342/adv7343 accept horizontal and vertical sync signals. a coincident low transition of both hsync and vsync inputs indicates the start of an odd field. a vsync low transition when hsync is high indicates the start of an even field. the ADV7342/adv7343 automatically blank all normally blank lines as per ccir-624. hsync and vsync are input on the s_hsync and s_vsync pins, respectively.
ADV7342/adv7343 rev. 0 | page 78 of 88 522 523 524 525 9 10 11 20 21 22 displ a y displ a y vertical blank odd field even field 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank 5 7 6 4 3 2 1 8 hsync vsync hsync vsync 0 6399-108 figure 107. sd slave mode 2, ntsc 622 623 624 625 21 22 23 display vertical blank odd field even field displ a y 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field display 320 7 6 5 4 3 2 1 hsync vsync hsync vsync 06399-109 figure 108. sd slave mode 2, pal mode 2master option (subadd ress 0x8a = x x x x x 1 0 1) in this mode, the ADV7342/adv7343 can generate horizontal and vertical sync signals. a coincident low transition of both hsync and vsync inputs indicates the start of an odd field. a vsync low transition when hsync is high indicates the start of an even field. the ADV7342/adv7343 automatically blank all normally blank lines as per ccir-624. hsync and vsync are output on the s_hsync and s_vsync pins, respectively. cb y pixel data hsync vsync pal = 132 clock/2 ntsc = 122 clock/2 y cr 06399-110 figure 109. sd timing mode 2, even-t o-odd field transition (master/slave)
ADV7342/adv7343 rev. 0 | page 79 of 88 cb pixel data hsync vsync pal = 132 clock/2 ntsc = 122 clock/2 pal = 864 clock/2 ntsc = 858 clock/2 cb y y cr 06399-111 figure 110. sd timing mode 2 odd-to-even field transition (master/slave) mode 3master/slave option (subaddress 0x 8a = x x x x x 1 1 0 or x x x x x 1 1 1) in this mode, the ADV7342/adv7343 accept or generate ho rizontal sync and odd/even field signals. when hsync is high, a transition of the field input indicates a new frame, that is, vertical retrace. the ADV7342/adv7343 automatically blank all normally blank lines as per ccir-624. hsync and vsync are output in master mode and input in slave mode on the s_vsync and s_vsync pins, respectively. 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank 522 523 524 525 9 10 11 20 21 22 display displ a y vertical blank odd field even field hsync field hsync field 8 7 6 5 4 3 2 1 0 6399-112 figure 111. sd timing mode 3, ntsc 622 623 624 625 5 6 21 22 23 displ a y vertical blank odd field even field field displ a y 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field field display 320 4 3 2 1 7 hsync hsync 06399-113 figure 112. sd timing mode 3, pal
ADV7342/adv7343 rev. 0 | page 80 of 88 appendix 6hd timing vertical blanking interval displ a y 1124 1125 1 2 5 6 7 8 21 4 3 20 22 560 field 1 field 2 vertical blanking interval display 561 562 563 564 567 568 569 570 584 566 565 583 585 1123 p_hsync p_vsync p_hsync p_vsync 06399-114 figure 113. 1080i hsync and vsync input timing
ADV7342/adv7343 rev. 0 | page 81 of 88 appendix 7video output levels sd yprpb output levelssmpte/ebu n10 pattern: 100% color bars 300mv 700mv white yellow cyan green magent a red blue black 06399-115 figure 114. y levelsntsc white yellow cyan green magenta red blue black 700mv 06399-116 figure 115. pr levelsntsc white yellow cyan green magenta red blue black 700mv 06399-117 figure 116. pb levelsntsc 700mv 3 00m v white yellow cyan green magenta red blue black 06399-118 figure 117. y levelspal white yellow cyan green magenta red blue black 700mv 06399-119 figure 118. pr levelspal white yellow cyan green magenta red blue black 700mv 06399-120 figure 119. pb levelspal
ADV7342/adv7343 rev. 0 | page 82 of 88 ed/hd yprpb output levels input code 940 64 eia-770.2, standard fo r y output voltage 300mv 700mv 700mv 960 64 eia-770.2, standard for pr/pb output voltage 512 06399-121 figure 120. eia-770.2 standard output signals (525p/625p) 782mv 714mv 286mv 700mv input code 940 64 eia-770.1, standard fo r y output voltage 960 64 eia-770.1, standard for pr/pb output voltage 512 0 6399-122 figure 121. eia-770.1 standard output signals (525p/625p) 300mv input code 940 64 eia-770.3, st a ndard for y output voltage 700mv 700mv 600mv 960 64 eia-770.3, standard for pr/pb output voltage 512 06399-123 figure 122. eia-770.3 standard output signals (1080i/720p) 300mv 300mv 700mv 700mv input code 1023 64 y?output levels fo r full input selection output voltage 1023 64 pr/pb?output levels for full input selection output voltage input code 06399-124 figure 123. output levels for full input selection
ADV7342/adv7343 rev. 0 | page 83 of 88 sd/ed/hd rgb output levels pattern: 100%/75% color bars 700mv/525mv 700mv/525mv 700mv/525mv 300mv 300mv 300mv r g b 06399-125 figure 124. sd/ed rgb output levelsrgb sync disabled 700mv/525mv 700mv/525mv 700mv/525mv 300mv r g b 0mv 300mv 0mv 300mv 0mv 06399-126 figure 125. sd/ed rgb output levelsrgb sync enabled 700mv/525mv 700mv/525mv 700mv/525mv 300mv 300mv 300mv r g b 06399-127 figure 126. hd rgb output levelsrgb sync disabled 300mv 0mv 0mv 700mv/525mv 700mv/525mv 700mv/525mv 300mv r g b 600mv 300mv 0mv 600mv 600mv 0 6399-128 figure 127. hd rgb output levelsrgb sync enabled
ADV7342/adv7343 rev. 0 | page 84 of 88 sd output plots 0.5 0 apl = 44.5% 525 line ntsc slow clamp to 0.00v at 6.72 s 10 20 f1 l76 30 40 50 60 100 50 0 ?50 0 volts ire:flt microseconds precision mode off synchronous sync = a frames selected 1, 2 06399-129 figure 128. ntsc color bars (75%) 0 noise reduction: 15.05db a pl = 44.3% 525 line ntsc no filtering slow clamp to 0.00v at 6.72 s 10 20 30 40 50 60 microseconds precision mode off synchronous sync = source frames selected 1, 2 f2 l238 50 0 0 ire:flt 0.6 0.4 0.2 0 ?0.2 volts 06399-130 figure 129. ntsc luma 0 noise reduction: 15.05db apl needs sync source. 525 line ntsc no filtering slow clamp to 0.00 at 6.72s 10 20 f1 l76 30 40 50 60 50 ?50 0 0.4 0.2 0 ?0.2 ?0.4 precision mode off synchronous sync = b frames selected 1, 2 volts ire:flt microseconds 06399-131 figure 130. ntsc chroma volts noise reduction: 0.00db a pl = 39.1% 625 line ntsc no filtering s low clamp to 0.00 at 6.72s 10 020 l608 30 40 50 60 0.4 0.2 0.6 0 ?0.2 precision mode off synchronous sound-in-sync off frames selected 1, 2, 3, 4 microseconds 06399-132 figure 131. pal color bars (75%) volts apl needs sync source. 625 line pal no filtering slow clamp to 0.00 at 6.72s 10 020 l575 30 40 50 60 0 0.5 microseconds 70 no bunch signal precision mode off synchronous sound-in-sync off frames selected 1 0 6399-133 figure 132. pal luma volts apl needs sync source. 625 line pal no filtering slow clamp to 0.00 at 6.72s 10 020 l575 30 40 50 60 0 0.5 ?0.5 no bunch signal precision mode off synchronous sound-in-sync off frames selected 1 microseconds 06399-134 figure 133. pal chroma
ADV7342/adv7343 rev. 0 | page 85 of 88 appendix 8video standards f v h* f f 272t 4t *1 4t 1920t eav code sav code digital active line 4 clock 4 clock 2112 2116 2156 2199 0 44 188 192 2111 0 0 0 0 0 0 0 0 f f f v h* c b c r c r y y fvh* = fvh and parity bits sav/eav: line 1?562: f = 0 sav/eav: line 563?1125: f = 1 sav/eav: line 1?20; 561?583; 1124?1125: v = 1 sav/eav: line 21?560; 584?1123: v = 0 for a frame rate of 30hz: 40 samples for a frame rate of 25hz: 480 samples input pixels a nalog waveform sample number smpte 274m digital horizontal blanking ancillary data (optional) or blanking code 0 h datum 06399-135 figure 134. eav/sav input data timing diagram (smpte 274m) y eav code ancillary data (optional) sav code digital active line 719 723 736 799 853 0 fvh* = fvh and parity bits sav: line 43?525 = 200h sav: line 1?42 = 2ac eav: line 43?525 = 274h eav: line 1?42 = 2d8 4 clock 4 clock 857 719 0 h datum digital horizontal blanking 0 0 0 0 0 0 0 0 c b c r c r y y f v h* smpte 293m input pixels a nalo g waveform sample number f f f f f v h* 06399-136 figure 135. eav/sav input data timing diagram (smpte293m) vertical blank 52252352452512567891213141516424344 active video active video 06399-137 figure 136. smpte 293m (525p)
ADV7342/adv7343 rev. 0 | page 86 of 88 622 623 624 625 10 11 43 44 45 4 vertical blank active video active video 12 56789 12 13 06399-138 figure 137. itu-r bt.1358 (625p) 747 748 749 750 26 27 25 744 745 displ a y vertical blanking interval 12 3 456 7 8 06399-139 figure 138. smpte 296m (720p) displ a y 1124 1125 21 4 3 20 22 560 field 1 display 561 562 563 564 567 568 569 570 584 566 565 583 585 1123 field 2 vertical blanking interval vertical blanking interval 12 5678 0 6399-140 figure 139. smpte 274m (1080i)
ADV7342/adv7343 rev. 0 | page 87 of 88 outline dimensions compliant to jedec standards ms-026-bcd 051706-a top view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc lead pitch 12.20 12.00 sq 11.80 pin 1 1.60 max 0.75 0.60 0.45 10.20 10.00 sq 9.80 view a 0.20 0.09 1.45 1.40 1.35 0.08 coplanarity view a rotated 90 ccw seating plane 0 . 1 5 0 . 0 5 7 3.5 0 figure 140. 64-lead low profile quad flat package [lqfp] (st-64-2) dimensions shown in millimeters ordering guide model temperature range macrovision 1 antitaping package description package option ADV7342bstz 2 ?40c to +85c yes 64-lead low profile quad flat package [lqfp] st-64-2 adv7343bstz 2 ?40c to +85c no 64-lead low profile quad flat package [lqfp] st-64-2 eval-ADV7342ebz 2 yes ADV7342 evaluation platform eval-adv7343ebz 2 no adv7343 evaluation platform 1 macrovision-enabled ics require the buyer to be an approved licensee (authorized buyer) of ics that are able to output macrovi sion rev 7.1.l1-compliant video. 2 z = pb-free part.
ADV7342/adv7343 rev. 0 | page 88 of 88 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06399-0-10/06(0)

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